Patents by Inventor Ming-An HSU

Ming-An HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250039356
    Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coding system derives multiple prediction linear models based on luma and chroma samples neighboring the current block. The video coding system constructs a composite linear model based on the multiple prediction linear models. The video coding system applies the composite linear model to incoming or reconstructed luma samples of the current block to generate a chroma predictor of the current block. The video coding system uses the chroma predictor to reconstruct chroma samples of the current block or to encode the current block.
    Type: Application
    Filed: December 29, 2022
    Publication date: January 30, 2025
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Yu-Ling HSIAO, Man-Shu CHIANG, Chih-Wei HSU, Olena CHUBACH, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250040334
    Abstract: The present disclosure provides a photoelectric device module and a manufacturing method thereof. The photoelectric device module includes a circuit module and a photoelectric conversion module. The circuit module includes a first electrode. The photoelectric conversion module is disposed on the circuit module, in which the photoelectric conversion module includes a second electrode, a photoactive layer, a light-transmitting electrode, and a light-transmitting substrate. The second electrode is electrically connected to the first electrode. The photoactive layer is disposed on the second electrode. The light-transmitting electrode is disposed on the photoactive layer. The light-transmitting substrate is disposed on the light-transmitting electrode.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 30, 2025
    Inventors: Yi-Ming CHANG, Cheng-En TSAI, Chung-Wei HSU
  • Patent number: 12210188
    Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
  • Patent number: 12210200
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 12211811
    Abstract: An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: January 28, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, Chien-Chou Tseng, Chih-Chia Chang, Kuan-Chu Wu, Yu-Lin Hsu
  • Patent number: 12212926
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: January 28, 2025
    Assignee: FORTEMEDIA, INC.
    Inventors: Wen-Shan Lin, Chun-Kai Mao, Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Nai-Hao Kuo
  • Patent number: 12211888
    Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Chi-Mao Hsu, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Hsin-Fu Huang
  • Patent number: 12211455
    Abstract: A display device, including a display module, a photodetector, a processor, and an optical structure layer, is provided. The display module is used for displaying an image. The photodetector is electrically connected to the display module and is used for detecting brightness of an ambient light and outputting a sensing signal. The processor is electrically connected to the display module and the photodetector, and is used for receiving the sensing signal and outputting a command signal to the display module according to the sensing signal, so that the display module adjusts brightness of the image according to the command signal. The optical structure layer is disposed on the display module. A glossiness of the optical structure layer is between 4 GU and 35 GU, and a reflectivity of specular component included (SCI) of the optical structure layer is between 3% and 6%.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: January 28, 2025
    Assignee: Innolux Corporation
    Inventors: Yu-Chun Hsu, Wei-Ming Chu, Sheng-Nan Fan
  • Publication number: 20250031441
    Abstract: A semiconductor device includes a plurality of first nanosheets of a first conductive type, a plurality of second nanosheets of a second conductive type and a gate structure. The gate structure wraps the first nanosheets and the second nanosheets, wherein a first thickness of at least one of the first nanosheets is smaller than a second thickness of at least one of the second nanosheets.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ming CHANG, Che-Chia Hsu, Kao-Ting Lai, Jhon Jhy Liaw
  • Patent number: 12205819
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Ting-Hung Hsu, Jia-Ni Yu, Wei-Hao Wu, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12205905
    Abstract: A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 21, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 12207052
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate. The opening portion of the substrate is under the diaphragm, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a pillar structure connected with the backplate and the diaphragm and a protection post structure extending from the backplate into the air gap. From a top view of the backplate, the protection post structure surrounds the pillar structure.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: January 21, 2025
    Assignee: FORTEMEDIA, INC.
    Inventors: Chun-Kai Mao, Chih-Yuan Chen, Feng-Chia Hsu, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
  • Patent number: 12206000
    Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.
    Type: Grant
    Filed: January 18, 2024
    Date of Patent: January 21, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
  • Publication number: 20250024072
    Abstract: A method and apparatus for video coding system that uses intra prediction based on cross-colour linear model are disclosed. According to the method, model parameters for a first-colour predictor model are determined and the first-colour predictor model provides a predicted first-colour pixel value according to a combination of at least two corresponding reconstructed second-colour pixel values. According to another method, the first-colour predictor model provides a predicted first-colour pixel value based on a second degree model or higher of one or more corresponding reconstructed second-colour pixel values. First-colour predictors for the current first-colour block are determined according to the first-colour prediction model. The input data are then encoded at the encoder side or decoded at the decoder side using the first-colour predictors.
    Type: Application
    Filed: October 26, 2022
    Publication date: January 16, 2025
    Inventors: Olena CHUBACH, Ching-Yeh CHEN, Tzu-Der CHUANG, Chun-Chia CHEN, Man-Shu CHIANG, Chia-Ming TSAI, Yu-Ling HSIAO, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20250023604
    Abstract: The application discloses a device and method for beamforming. The beamforming method comprises: sending a null data packet announcement (NDPA) frame from a beamformer to a pseudo user and a target user to indicate the target user to prepare for channel estimation; sending a null data packet (NDP) from the beamformer to the target user and performing channel estimation by the target user based on the NDP to determine channel state information; sending a beamforming report poll (BRP) trigger frame from the beamformer to the target user to trigger the target user to feed back channel state information; and sending from the target user a beamforming report to the beamformer, wherein the beamforming report including the channel state information.
    Type: Application
    Filed: June 14, 2024
    Publication date: January 16, 2025
    Inventors: Li-Chieh CHEN, Cheng-En HSIEH, Wei-Hsu CHEN, Ming-Hsiang TSENG, Kang-Li WU
  • Patent number: 12198873
    Abstract: The invention discloses an illuminated keyswitch structure, which includes a base plate, a keycap, and a plurality of light-emitting dies. The base plate has a through hole. The keycap is movably disposed above the base plate in a vertical direction. The light-emitting dies are disposed under the keycap. The light-emitting dies are not higher than the base plate. The light-emitting dies are located within a projection of the through hole in the vertical direction. At least two of the light-emitting dies are arranged parallel to an hole edge of the through hole. In the illuminated keyswitch structure of the invention, distances from the light-emitting dies that are arranged parallel to the hole edge to the hole edge are close to each other, and light of different colors emitted by said light-emitting dies travels through the hole edge at similar distances, thereby suppressing uneven light mixing and color deviation.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: January 14, 2025
    Assignees: DARFON ELECTRONICS (HUAIAN) CO., LTD., DARFON ELECTRONICS CORP.
    Inventors: Yu-Chuan Ku, Wen-Ming Hsu, Yuming Huang
  • Patent number: 12191401
    Abstract: Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.
    Type: Grant
    Filed: January 18, 2024
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Ming Hsu, Yi-Jing Li, Chih-Hsin Ko, Kuang-Hsin Chen, Da-Wen Lin, Clement Hsingjen Wann
  • Patent number: 12159930
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: December 3, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20240387278
    Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction; a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction; a first isolation structure extending into the interlayer dielectric, disposed between the first and second source/drain structures, and disposed next to a gate structure along the first direction; and a second isolation structure below the first and second conduction channels. The second isolation structure includes a shallow trench isolation structure.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Ching-Feng Fu, Huan-Just Lin, Che-Ming Hsu
  • Publication number: 20240379419
    Abstract: A semiconductor structure includes a gate, a self-aligned contact (SAC) layer that is disposed on the gate and that has a seam at a top surface of the SAC layer, a gate spacer that is formed on a sidewall of the gate, and a metal contact that is disposed adjacent to the gate spacer and that is spaced apart from the gate by the gate spacer. The SAC layer includes a filler that seals the seam in the SAC layer, and a top surface of the filler is coplanar with a top surface of the gate spacer and a top surface of the metal contact.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Ching-Feng FU, Huan-Just LIN, Che-Ming HSU