Patents by Inventor Ming-An HSU

Ming-An HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107117
    Abstract: A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 27, 2025
    Inventors: CHUNG-HSIUNG HO, CHI-HSUEH LI, CHIA-WEI CHEN, YU-MING HSU, WEN-LIANG HUANG, MING-KUN HSIN, SHIH-MING CHEN
  • Patent number: 12257708
    Abstract: A three-dimensional measuring device includes a ball-shaped structure, an X-axis measuring module, a Y-axis measuring module and a Z-axis measuring module. The ball-shaped structure is moved and/or rotated in response to a movement of a movable object. The X-axis measuring module includes a first measuring structure and a first position sensor. The first measuring structure is movable along an X-axis direction and contacted with the ball-shaped structure. The Y-axis measuring module includes a second measuring structure and a second position sensor. The second measuring structure is movable along a Y-axis direction and contacted with the ball-shaped structure. The Z-axis measuring module includes a third measuring structure and a third position sensor. The third measuring structure is movable along a Z-axis direction and contacted with the ball-shaped structure.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: March 25, 2025
    Assignee: Delta Electronics, Inc.
    Inventors: Chi-Huan Shao, Chih-Ming Hsu, Chi-Shun Chang, Hung-Sheng Chang
  • Publication number: 20250098226
    Abstract: Present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor fin and a metal gate. The semiconductor fin has a first portion and a second portion over the first portion. A height of the second portion is greater than a width of the second portion. The metal gate has a bottom portion, an upper portion, and a lateral portion connecting the bottom portion and the upper portion. The bottom portion is between the first portion and the second portion of the semiconductor fin, and the upper portion is over the second portion of the semiconductor fin.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: CHIA-MING HSU, YI-JING LI, CHIH-HSIN KO, KUANG-HSIN CHEN, DA-WEN LIN, CLEMENT HSINGJEN WANN
  • Publication number: 20250096470
    Abstract: An electronic device includes a casing, an antenna, and a connector. The casing includes a metal layer and a first slot and a second slot located on the metal layer. The metal layer includes a metal connecting segment, a first region, and a second region. The metal connecting segment is located between the first slot and the second slot, and the first region and the second region are separated by the first slot, the second slot, and the metal connecting segment. The antenna is connected to the first region, and the antenna is adapted to resonate at a frequency band. The connector is connected to the second region.
    Type: Application
    Filed: July 2, 2024
    Publication date: March 20, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Chang-Hsun Wu, Ming-Huang Chen, Yu-Peng Lin, Hung-Cheng Tsai, Kuo-Yung Chiu, Hsuan-Chi Lin, Chao-Hsu Wu
  • Publication number: 20250096000
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.
    Type: Application
    Filed: October 16, 2023
    Publication date: March 20, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Kun-Ju Li, Hsin-Jung Liu, Jhih Yuan Chen, I-Ming Lai, Ang Chan, Wei Xin Gao, Hsiang Chi Chien, Hao-Che Hsu, Chau Chung Hou, Zong Sian Wu
  • Patent number: 12255150
    Abstract: The current disclosure describes techniques for making an alignment mark on a wafer. A recess is etched in a first surface region of a wafer. A device structure is formed in a second surface region of the wafer. A dielectric layer is deposited on the first surface of the wafer and filling the recess. A first planarization procedure is conducted to planarize the dielectric layer. After the first planarization procedure, a second planarization procedure is conducted to device structures on the second surface region of the wafer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Jen Hsu, Jheng-Si Su, Kung-Ming Liu, Tzuyi Hsieh, Feng-Inn Wu
  • Patent number: 12253960
    Abstract: The invention provides method and system for improving efficiency of protecting multi-content process. The system may cooperate with a memory, and may comprise one or more hardware IPs (intellectual properties) for content processing, one of the one or more IPs may be associated with multiple access identities. The memory may comprise multiple different ranges, each range may register an access of one of the multiple access identities as a permissible access. The method may comprise: selecting one of the access identities for processing a first content, and using the selected access identity when said IP accesses the memory during processing of the first content; selecting a different one of the access identities for processing a second content, and using the selected different access identity when said IP accesses the memory during processing of the second content.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 18, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yu-Tien Chang, Lin-Ming Hsu, Chun-Ming Chou
  • Patent number: 12254257
    Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Cheng Syu, Po-Zeng Kang, Yung-Hsu Chuang, Shu-Chin Tai, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 12255392
    Abstract: A wideband antenna system includes a first metal radiation portion, having a coupling distance with a second metal radiation portion; a first feeding contact and a second feeding contact, electrically connected to the first metal radiation portion and the second metal radiation portion respectively, and close to the coupling distance; a first ground contact, electrically connected to the second metal radiation portion; a second ground contact, electrically connected to the first metal radiation portion; an impedance tuner, electrically connected to the first feeding contact, the second feeding contact, the first ground contact, the second ground contact, and a radio frequency signal source, to switch the first metal radiation portion and the second metal radiation portion; an aperture contact, electrically connected to the first metal radiation portion; and an aperture tuner, electrically connected to the aperture contact.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: March 18, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Chieh Su, Wei-Cheng Lo, Chien-Ming Hsu, Che-Yen Lin, Chuan-Chien Huang
  • Patent number: 12255104
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Publication number: 20250086377
    Abstract: An electronic device and a non-transitory computer-readable storage medium are provided. The electronic device includes a storage module and a processing module. The processing module loads at least one program instruction to perform the following steps: parsing a plurality of cells in an analysis region of a data sheet to identify each cell as one of at least one formula cell and at least one non-formula cell; classifying, according to a formula expression of at least one formula cell, the at least one formula cell to at least one formula group; selectively establishing a side label category tree, a top label category tree, and a master category tree according to the at least one formula group; establishing a database data model according to the side label category tree, the top label category tree, and the master category tree; and converting each formula expression into a structure reference form.
    Type: Application
    Filed: December 20, 2023
    Publication date: March 13, 2025
    Applicant: POTIX CORPORATION
    Inventors: Chih-Heng Chen, Jen-Feng Chao, Wenning Hsu, Ming-Shia Yeh
  • Publication number: 20250087906
    Abstract: An antenna-in-module includes a ground plate, three radiating elements, and two feed stubs. A first radiating element and a ground plate are arranged at an interval along a Z-axis and are disposed opposite to each other. The first radiating element and a second radiating element are arranged at an interval along an X-axis. A first gap between the first radiating element and the second radiating element extends along a Y-axis. A third radiating element and the second radiating element are arranged at an interval along the Z-axis and are disposed opposite to each other. At least a part of a first feed stub is disposed in a first aperture that includes space between the first gap and the ground plate. At least a part of a second feed stub is disposed in a second aperture that includes space between the second radiating element and the third radiating element.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 13, 2025
    Inventors: Chen-Fang Tai, Chih-Wei Hsu, Chien-Ming Lee, En Tso Yu, Chih Yu Tsai
  • Publication number: 20250080756
    Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 6, 2025
    Inventors: Man-Shu CHIANG, Olena CHUBACH, Yu-Ling HSIAO, Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250080794
    Abstract: A projection system, a projection device and a control method thereof are provided.
    Type: Application
    Filed: September 2, 2024
    Publication date: March 6, 2025
    Applicant: Coretronic Corporation
    Inventors: Yu-Meng Chen, Yi Wei Hsu, Wei-Hsin Kan, Ssu-Ming Chen
  • Publication number: 20250081730
    Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.
    Type: Application
    Filed: June 26, 2024
    Publication date: March 6, 2025
    Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
  • Publication number: 20250078897
    Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.
    Type: Application
    Filed: October 5, 2023
    Publication date: March 6, 2025
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chen Yang Tang, Hsuan Ming Kuo, Shi-Chieh Hsu, Wei Lin
  • Publication number: 20250079314
    Abstract: An interconnect structure includes a conductive feature embedded in a dielectric feature. The conductive feature has a first horizontal portion and a first vertical portion. The first horizontal portion extends in a horizontal direction to terminate at two edge surfaces. The first horizontal portion includes graphene layers stacked on each other, and an intercalation material interposed among the graphene layers. The intercalation material includes a first atom dopant including one of a group 1 metal, a group 2 metal, a group 3 metal, a lanthanide series metal, an actinide series metal, and combinations thereof. The first vertical portion extends in a vertical direction and is in contact with one of the two edge surfaces of the first horizontal portion. The first vertical portion is made of a first electrically conductive metal material.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hans HSU, Shu-Wei LI, Yu-Chen CHAN, Shin-Yi YANG, Ming-Han LEE, Blanka MAGYARI-KOPE
  • Publication number: 20250079246
    Abstract: A chip package structure is provided. The chip package structure includes a semiconductor die formed over a package substrate and an interconnect structure bonded and electrically connected between the semiconductor die and the package substrate. The chip package structure also includes a stiffener structure formed over the package substrate and covering the semiconductor die. The metal stiffener structure has a metal lid cap portion covering the upper surface of the semiconductor die, a metal ring portion surrounding the metal lid cap portion, and a metal spacer wall portion extending between the metal ring portion and the package substrate to surround the semiconductor die.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Inventors: Chieh-Ming CHANG, Chia-Kuei HSU, Ming-Chih YEW, Shin-Puu JENG
  • Publication number: 20250071288
    Abstract: A method and apparatus for video coding are disclosed. According to the method for the decoder side, encoded data associated with a current block comprising a first-colour block and a second-colour block are received. An inherited model parameter set is determined from a previously coded block coded in a first CCLM related mode, wherein the inherited model parameter set comprises a first scaling parameter associated with the first CCLM related mode. A final inherited model parameter set is derived if an update value for the inherited model parameter set is determined, where the final inherited model parameter set is determined based on the first scaling parameter and the update value. Then, the encoded data associated with the second-colour block are decoded using prediction data based on an updated CCLM related model associated with the final inherited model parameter set. A method and apparatus for the encoder side are also disclosed.
    Type: Application
    Filed: January 18, 2023
    Publication date: February 27, 2025
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG
  • Publication number: 20250071331
    Abstract: A method and apparatus for video coding are disclosed. According to the method for the decoder side, a first syntax, related to whether the current block is coded in a CCLM related mode, is parsed from a bitstream comprising the encoded data for the current block. If the first syntax indicates the current block being coded in the CCLM related mode, a second syntax is parsed from the bitstream, wherein the second syntax is related to whether a multiple model CCLM mode is used or whether one or more model parameters are explicitly signalled or implicitly derived. The model parameters for the second-colour block are determined if the first syntax indicates the current block being coded in a CCLM related mode. The encoded data associated with the second-colour block is then decoded using prediction data comprising the cross-colour predictor for the second-colour block.
    Type: Application
    Filed: January 18, 2023
    Publication date: February 27, 2025
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG