Abstract: A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.

Abstract: An electronic device includes a substrate, a first transistor and a second transistor. The first transistor is disposed on the substrate and has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second transistor is disposed on the substrate and has a first terminal electrically connected to the second terminal of the first transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first transistor. Wherein a voltage value of the first voltage level is greater than a voltage value of the second voltage level.

Abstract: Provided is a semiconductor device including a first transistor of a first type comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second transistor of the first type comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.

Abstract: An offshore wind turbine with anti-accumulation of aquatic organisms, comprising: a base with an interior space, the base being made of conductive material; a tower incorporated above the base; a nacelle, connected to the tower; a plurality of blades, each interconnected with the nacelle; and a power supply system electrically connected to the base and disposed within the interior space, the power supply system being used to provide electrical energy to the base to energize the surface of the base to form an electric field.

Abstract: A vertical probe includes opposite first and third sides, and opposite second and fourth sides. The third and fourth sides extend in a planar manner from a body to a tip portion. The first and second sides include first and second upper plane segments at the body, first and second transition segments at the tip portion, and first and second lower plane segments closer to the third and fourth sides than the first and second upper plane segments are, respectively. The first and second transition segments gradually approach the third and fourth sides as they extend from the first and second upper plane segments to the first and second lower plane segments. The first transition and lower plane segments are realized by laser processing. The vertical probe can contact small conductive contacts with good current resistance, structural strength, lifespan, and processing accuracy. When applied to a probe head, breaking or shifting position of the tip portion due to vertical movement can be avoided.

Abstract: A codebook generation method and an electronic apparatus are provided. The codebook generation method includes: collecting a plurality of pieces of electric field information of a plurality of antenna units in at least one millimeter-wave antenna module based on an initial codebook; correspondingly generating a full chain codebook (Full Chain Codebook) based on the electric field information; then, extendedly generating a sub chain codebook (Sub Chain Codebook) based on the full chain codebook; and finally generating, based on the full chain codebook and the sub chain codebook, an optimized codebook (Optimized Codebook) by using a power saving algorithm or a cumulative distribution function 50% gain loss algorithm. Therefore, the electronic apparatus using the optimized codebook is more excellent in power saving efficiency and overall efficiency performance.

Abstract: A method for cleaning is provided. The method includes: removing a pellicle frame from a top surface of a photomask by debonding an adhesive between the photomask and the pellicle frame, wherein a first portion of the adhesive is remained on the top surface of the photomask, and removing the first portion of the adhesive on the top surface of the photomask, including applying an alkaline solution to the top surface of the photomask, and performing a mechanical impact to the photomask.

Abstract: An illuminated keyswitch structure includes a base plate, a keycap, and a light-emitting die package. The light-emitting die package is disposed to illuminate the keycap through the base plate. The light-emitting die package comprises a warm color temperature light-emitting die and a cold color temperature light-emitting die, and the light-emitting die package extends along an arrangement direction. Each of the two light-emitting dies has a short side arranged adjacent to each other, with a long side of each of the two light-emitting dies facing a same direction and configured proximate to each other. A gap between the two adjacent short sides of the two light-emitting dies is not greater than either one of the two adjacent short sides of the two light-emitting dies.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, strained layers, source/drain contact patterns, a gate contact via, and source/drain contact vias. The gate structure is disposed over the semiconductor substrate. The strained layers are disposed aside the gate structure. The source/drain contact patterns are disposed on and electrically connected to the strained layers. Top surfaces of the source/drain contact patterns are coplanar with a top surface of the gate structure. The gate contact via is disposed on and electrically connected to the gate structure. The source/drain contact vias are disposed on and electrically connected to the source/drain contact patterns.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.

Abstract: A casing latch structure is disclosed and includes a casing, a main body, a clamping element, a fastening element, and an abutting element. The casing includes a first wall and a second wall perpendicular to each other, a through hole disposed on the first wall, and a sliding groove disposed on the second wall. The main body includes a clamping portion, a sliding portion and a fastened portion. The sliding portion is connected between the clamping portion and the fastened portion arranged on two opposite sides of the second wall, and received in the sliding groove. The clamping element is sleeved between the sliding portion and the fastened portion. The fastening element is engaged with the fastened portion to lock or release the clamping portion. The abutting element includes an abutting portion and an embedded portion connected to each other and corresponding to the through hole and the sliding groove.

Abstract: A micro-electro-mechanical system (MEMS) microphone is provided. The MEMS microphone includes a substrate, a backplate, an insulating layer, and a diaphragm. The substrate has an opening portion. The backplate is disposed on a side of the substrate, with protrusions protruding toward the substrate. The diaphragm is movably disposed between the substrate and the backplate and spaced apart from the backplate by a spacing distance. The protrusions are configured to limit the deformation of the diaphragm when air flows through the opening portion.

Abstract: A display device including a display module and an optical structure layer is provided. The display module is used for displaying an image. The optical structure layer is disposed on the display module, and comprises an anti-glare layer and an anti-reflection layer, wherein the anti-reflection layer is disposed on the anti-glare layer. A glossiness of the optical structure layer is between 4 GU and 35 GU, and a reflectivity of specular component included (SCI) of the optical structure layer is between 3% and 6%.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: A high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation layer and the mesa structure. The mesa structure includes a channel layer, a barrier layer on the channel layer, two opposite first edges extending along a first direction, and two opposite second edges extending along a second direction. The contact structure includes a body portion and a plurality of protruding portions. The body portion penetrates through the passivation layer. The protruding portions penetrate through the barrier layer and a portion of the channel layer. In a top view, the body portion overlaps the two opposite first edges of the mesa structure without overlapping the two opposite second edges of the mesa structure.

Abstract: A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.