Patents by Inventor Ming An

Ming An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171775
    Abstract: An input 3D point cloud including a spatial distribution of points is received. Patches including pre-reshaped patch data are generated from the input 3D point cloud. Encoder-side reshaping is performed on the pre-reshaped patch data to generate reshaped patch data for the patches. The reshaped patch data is encoded into a 3D video signal, which a recipient device of the 3D video signal can decode to generate a reconstructed 3D point cloud that approximates the input 3D point cloud.
    Type: Application
    Filed: May 16, 2022
    Publication date: May 23, 2024
    Applicant: Dolby Laboratories Licensing Corporation
    Inventors: Guan-Ming SU, Peng YIN
  • Publication number: 20240168254
    Abstract: An imaging lens assembly includes a lens barrel, optical lens elements, an annular retaining element and a nano-microstructure. The optical lens elements include at least one optical lens element disposed in the lens barrel. The annular retaining element is physically contacted with the optical lens element, and the annular retaining element includes an object-side surface, an image-side surface, an outer diameter surface and a light-through hole. The outer diameter surface is connected to the object-side surface and the image-side surface. The light-through hole is formed by gradually tapering from the object-side surface and the image-side surface towards the optical axis. The nano-microstructure has a plurality of irregular ridged convexes. The nano-microstructure is located between a lens barrel area defined via the lens barrel and a lens element area defined via the optical lens element on a direction vertical to the optical axis.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 23, 2024
    Inventors: Ssu-Hsin LIU, Heng-Yi SU, Liang-Chieh WENG, Wen-Yu TSAI, Ming-Ta CHOU
  • Publication number: 20240172393
    Abstract: Methods and apparatus for immersion cooling systems are disclosed herein. An example apparatus includes a base plate, fins extending from the base plate, a tube extending along an axis through the fins, the tube including an inlet, and a slot extending along the axis, the inlet, the slot, and the fins sequentially defining a flow pathway.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 23, 2024
    Inventors: Sandeep Ahuja, Yang Yao, Ming Zhang, Yuehong Fan, Xiang Que, Mark MacDonald, Casey Jamesen Carte, Yue Yang, Eric D. McAfee, Satyam Saini, Suchismita Sarangi, Drew Damm, Jessica Gullbrand
  • Publication number: 20240171310
    Abstract: Embodiments of this application provide data processing methods, computer program products, computer-readable storage medium and apparatuses. In an embodiment, a method includes: inputting bits in a coded bitstream into a first interleaver, wherein the coded bitstream is allocated to a first resource unit (RU) for a first user, wherein the first RU comprises M RUs, and M is an integer greater than 1, and reordering the bits in the coded bitstream by using the first interleaver, wherein a number NSD of data subcarriers of the first interleaver is a positive integer within [NSD_min/Q, NSD_max/Q], wherein NSD_min is a sum of data subcarriers comprised in the first RU, NSD_max is a sum of subcarriers comprised in the first RU, and Q is a number of data subcarriers to which a bit is mapped.
    Type: Application
    Filed: January 29, 2024
    Publication date: May 23, 2024
    Inventors: Jian YU, Ming GAN
  • Publication number: 20240166566
    Abstract: Various embodiments include a system or platform that uses electrochemistry to upcycle waste products and low-value minerals into valuable, carbon dioxide (CO2)-neutral materials. Various embodiments may include systems and/or methods for processing material inputs using an electrochemical reactor. Various embodiments may include systems, methods, and/or devices for capturing and sequestering carbon dioxide (CO2) while producing valuable co-products.
    Type: Application
    Filed: April 5, 2022
    Publication date: May 23, 2024
    Applicant: Sublime Systems, Inc.
    Inventors: Jesse D. BENCK, Yet-Ming CHIANG, Leah D. ELLIS, Kyle DOMINGUEZ, Mariya LAYUROVA
  • Publication number: 20240170526
    Abstract: A back side illumination (BSI) image sensor includes an epitaxial substrate, a deep trench isolation (DTI) structure from one surface to the other surface of the epitaxial substrate, a buried oxide layer on the epitaxial substrate, an epitaxial layer, a well region, a floating diffusion (FD) region, a shallow trench isolation (STI) structure, and vertical transfer gates (VTGs). The buried oxide layer has openings exposing the epitaxial substrate, and the epitaxial layer is formed on the epitaxial substrate and covers the buried oxide layer. The well region is in the epitaxial layer and the epitaxial substrate. The FD region is in the well region above the buried oxide layer, and a width of the buried oxide layer is larger than that of the FD region. The STI structure is in the epitaxial layer. The VTGs are in the epitaxial layer and through the openings of the buried oxide layer.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 23, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Ping Chung, Saysamone Pittikoun, Chih-Hao Peng, Ming-Yu Ho
  • Publication number: 20240168266
    Abstract: An optical path folding element includes an optical portion, a connection portion, matte structures and a light blocking layer. The optical portion has an optical surface and two reflective surfaces. A light beam enters into the optical path folding element via the optical surface and is reflected inside the optical path folding element through the optical surface. Each reflective surface is configured to reflect the light beam again inside the optical path folding element. The connection portion has connection surfaces connected to the optical surface and the reflective surfaces. The matte structures are at least disposed on and integrally formed with the connection portion. Each unitary structure of the matte structures is tapered off and recessed from the connection portion, such that the outer surface of the connection portion has an undulating shape. The light blocking layer is at least disposed on the connection portion for blocking light.
    Type: Application
    Filed: October 3, 2023
    Publication date: May 23, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Chen Wei FAN, Syuan Ruei LAI, Jyun-Jia CHENG, Ming-Ta CHOU
  • Publication number: 20240169615
    Abstract: An electronic device and a non-transitory computer-readable storage medium are provided. The electronic device includes a storage module and a processing module. The storage module is configured to store at least one program instruction. The processing module is coupled to the storage module, and is configured to load the at least one program instruction to perform the following steps: parsing a plurality of cells in an analysis area in a data sheet to identify each of the cells as a formula cell or a non-formula cell; classifying the formula cells so that the formula cells having similar formula expressions fall into the same formula group; analyzing a formula structure of the formula expressions of each formula group to output at least one recommended chart option.
    Type: Application
    Filed: April 3, 2023
    Publication date: May 23, 2024
    Applicant: POTIX CORPORATION
    Inventors: Chih-Heng Chen, Jen-Feng Chao, Wenning Hsu, Ming-Shia Yeh
  • Publication number: 20240170414
    Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Chiang, Hsien-Ming Tu, Hao-Yi Tsai, Tin-Hao Kuo
  • Publication number: 20240165247
    Abstract: Provided are a conjugate formed between an anaesthetic compound and a peptide component of the amino acid sequence: W-Lys-X1-Ser-U-X2-Y, wherein: W, X1, U, X2 and Y are as defined in the description, as well as regioisomers, stereoisomers, and pharmaceutically- or cosmetically-acceptable salts of said conjugates, which conjugates are useful in the treatment of conditions characterised by inflammation and/or of pain. Preferred anaesthetics are local anaesthetics, such as procaine.
    Type: Application
    Filed: March 17, 2021
    Publication date: May 23, 2024
    Inventors: Ming GU, Maoqian SONG, Bengt Ingemar SAMUELSSON, Jan-Christer JANSON
  • Publication number: 20240171204
    Abstract: A multilane transmitter includes a plurality of transmitter lane circuits and a phase lock circuit. The phase lock circuit includes an oscillating circuit. The oscillating circuit is configured to provide clock signals corresponding to the transmitter lane circuits. The oscillating circuit includes a plurality of logic units. Clock receiving terminals of the transmitter lane circuits are coupled to an output terminal of one of the plurality of logic units.
    Type: Application
    Filed: February 21, 2023
    Publication date: May 23, 2024
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Tsung-Ming CHEN
  • Publication number: 20240171713
    Abstract: An illumination system that provides an illumination beam is provided. The illumination system includes a first light source module, a second light source module, a third light source module, a first optical element, a second optical element, and a third optical element. The first light source module and the second light source module provide a first color light beam, a second color light beam, and a third color light beam. The third light source module provides a third color light beam. The first optical element, the second optical element and the third optical element are disposed on transmission paths of the first color light beam, the second color light beam and the third color light beam, and the first light source module and the second light source module are respectively located on opposite sides of the first optical element and the second optical element.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 23, 2024
    Applicant: Coretronic Corporation
    Inventors: Kuan-Lun Chen, Kai-Jiun Wang, Ming-Tsung Weng, Shun-Tai Chen
  • Publication number: 20240170296
    Abstract: A method for forming a semiconductor structure includes forming strip patterns over a semiconductor substrate, forming a hard mask layer over the strip patterns, and forming a patterned photoresist layer over the hard mask layer. The patterned photoresist layer has a plurality of first openings. The method also includes etching the hard mask layer using the patterned photoresist layer. Remaining portions of the hard mask layer form a plurality of pillar patterns that are separated from one another. The method also includes depositing a dielectric layer along the plurality of pillar patterns, etching the dielectric layer to form a plurality of second openings, removing the plurality of pillar patterns to form a plurality of third openings in the dielectric layer, and etching the strip patterns using the dielectric layer as a mask.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 23, 2024
    Inventors: Hung-Jung YAN, Chun-Chieh WANG, Tzu-Ming OU YANG
  • Publication number: 20240171074
    Abstract: A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 23, 2024
    Inventors: Jiing-Horng Wang, Yu-Pin Tseng, Chia-Jung Chang, Tsan-He Wang, Shao-Ming Chang
  • Publication number: 20240165831
    Abstract: A joint assembly, a swing device and a robot are provided. The joint assembly includes a movable part defining a movable groove and a rotating part. The rotating part includes a rotating body being a spherical shape. The rotating body is rotatably received in the movable groove to adapt to the movable part. The rotating part defines an air hole with an air inlet and an air outlet. The air inlet is configured to receive introduced air, and the air outlet is configured to expel the air to the movable groove.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 23, 2024
    Inventors: ZHEN-XING LIU, XIAO-MING XU, BO LONG, ZHEN CHEN, YAN-CHUN ZHU
  • Publication number: 20240167149
    Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 23, 2024
    Inventors: Wen-Hao Cheng, Yen-Yu Chen, Yi-Ming Dai
  • Publication number: 20240170385
    Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 23, 2024
    Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Mei-Yen CHEN, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
  • Publication number: 20240170972
    Abstract: An electrical system includes a first conduction terminal, a second conduction terminal, N power units and N supporting devices. The N power units are electrically connected between the first conduction terminal and the second conduction terminal in series, and N is an integer greater than or equal to 2. Each of the N supporting devices includes a conductive part and a support part. Each of the N power units is disposed on the corresponding conductive part. The conductive part is electrically connected with a power terminal of one of the N power units or electrically connected with a reference potential of the electrical system. The support part is connected between the corresponding conductive part and a ground potential.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 23, 2024
    Inventors: Teng Liu, Jianxing Dong, Xiaohu Li, Ming Wang
  • Patent number: 11988817
    Abstract: An optical imaging system includes five lens elements, the five lens elements being, in order from an object side to an image side: a first lens element having positive refractive power; a second lens element having negative refractive power; a third lens element having positive refractive power; a fourth lens element having positive refractive power; and a fifth lens element having negative refractive power.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: May 21, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chien-Hsun Wu, Tzu-Chieh Kuo, Kuan-Ming Chen
  • Patent number: 11991888
    Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Yu Chang, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin