Abstract: A text-to-speech conversion system that includes a first module to convert text into words, a second module to convert words into phonemes, a third module to map phonemes to sound units, and a storage unit to store speech representations for a library of sound units. The first, second, and third modules and the storage unit are implemented within a single integrated circuit to reduce size and cost. The system typically further includes a ROM to store the codes for the modules, a RAM to store the text and intermediate results, a processor to execute the codes for the modules, a control module to direct the operation of the first, second, and third modules. The storage unit may be implemented with a multi-level, non-volatile analog storage array and may be programmed with a new library of speech representations by a programming module.

Abstract: A multilevel analog recording and playback system is described. An analog processing circuit processes analog data. A storage circuit includes a non-volatile memory array, a switching circuit, and a communication interface. The non-volatile memory array stores analog and digital data. The switching circuit transfers the analog and digital data to and from the memory array. The communication interface allows a processor to exchange information with the device.

Abstract: A method of forming a semiconductor memory having rows and columns of memory cells is as follows; forming a plurality of rows of program gate lines from a second layer polysilicon; forming a plurality of rows of select gate lines from a third polysilicon layer; forming a plurality of rows of diffusion source lines: forming a plurality of local bitlines from a first layer metal, the cells along each column being divided into a pre-designated number of groups, and drains of the cells in each group being connected to a local bitline extending across the cells in the group of cells; and forming a plurality of global bitlines from a second layer metal extending along every two columns of cells, each global bitline being configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A semiconductor memory includes a plurality of memory cells arranged along rows and columns, each cell having a floating gate, a drain region, a source region, a program gate terminal, and a select gate terminal. The program gate terminals of the cells along each row of cells are connected together forming a continuous program gate line. The select gate terminals of the cells along each row of cells are connected together forming a continuous select gate line. The source regions of the cells along each row of cells are connected together forming a continuous source line. The cells along each column are divided into a predesignated number of groups, and the drain regions of the cells in each group are connected to a local bitline extending across the cells in the group of cells. A global bitline extends along every two columns of cells, and is configured to selectively provide electrical connection to the local bitlines along the corresponding two columns of cells.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further Vcc scaling becomes possible.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

Abstract: A Flash EEPROM cell employing a sidewall polysilicon spacer as an erase gate. The cell is programmed by source side channel hot electron injection and erased by poly-to-poly tunneling through a poly tunnel oxide between the floating gate and the erase gate. The floating gate is defined by the control gate sidewall spacer which is formed before the floating gate poly self-aligned etch step. The polysilicon sidewall spacer erase gate is formed after growing a poly tunnel oxide on the sidewall of the floating gate poly. Since the poly tunnel oxide thickness is minimized, a fast programming with a low power consumption can be achieved. By using poly-to-poly tunneling erase scheme, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible.

Abstract: A virtual ground flash EEPROM array is based on a source-coupling, split-gate storage cell. The array includes a plurality of spaced-apart, parallel buried n+ bit lines formed in a P-type silicon substrate to define alternating source and drain lines that are segment-contacted. Field oxide islands formed in the array between adjacent source and drain lines define the substrate channel regions of the individual storage cell transistors. The poly 1 floating gate of each cell is formed over a first portion of the substrate channel region and is separated from the channel region by a layer of floating gate oxide. Each floating gate includes a tunnelling arm that extends over the cell's source line and is separated therefrom by thin tunnel oxide. A poly2 word line is formed over the floating gates of the storage cells in each row of the array. The poly2 word line is separated from the underlying floating gate by a layer of oxide/nitride/oxide (ONO).

Abstract: A method for forming an asymmetrical LDD structure is described. A polysilicon gate electrode is formed overlying a layer of gate silicon oxide on the surface of a semiconductor substrate. The surfaces of the semiconductor substrate and the gate electrode are oxidized to form a surface oxide layer. Polysilicon spacers are formed on the sidewalls of the gate electrode wherein one side of the gate electrode is a source side and the other side of the gate electrode is a drain side. The polysilicon spacer on the source side of the gate electrode is removed. First ions are implanted to form heavily doped source and drain regions within the semiconductor substrate not covered by the gate electrode and the polysilicon spacer on the drain side of the gate electrode. Then the drain side polysilicon spacer is removed.

Abstract: A selected cell in a virtual-ground flash EEPROM array, which is based on a source-coupled, split-gate storage cell, is programmed by grounding the source bit line of the selected cell, grounding the drain bit line of the immediately adjacent cell which shares the same source bit line, applying a write bias voltage to the remaining bit lines, applying a programming voltage to the word line associated with the selected cell, and applying ground to the remaining word lines.

Abstract: A method was achieved for making electrical connections to FET self-aligned source/drain areas extending the limits of the photolithographic resolution and relaxing the alignment tolerance. FET gate electrodes are formed by patterning a first polysilicon layer having a first insulating layer thereon. Lightly doped drains (LDDs) and insulating first sidewall spacers are then formed. A polycide layer (second polysilicon/silicide layer) having a second insulating thereon is then deposited and patterned. The new method involves etching the second insulating layer and partially into the polycide layer. After removing the photoresist, another dielectric layer is conformally deposited and then anisotropically etched back to form the second sidewall spacers. The remaining polycide layer is then etched using the second insulating layer and the second spacer as a hard mask. Thus, second poly extensions are formed over and onto the first poly and the field oxide.

Abstract: The present invention provides a self-aligned trench isolation scheme for the MOS select transistors in an alternate metal virtual ground (AMG) EPROM array architecture. The new isolation scheme allows bit line to bit line spacing to be scaled to 0.6 .mu.m and below without compromising either data retention or memory performance characteristics. A new poly stack self-aligned etch scheme is also provided to scale the word line spacing to 0.6 .mu.m and below and, thus, allow a 64 Mbit EPROM array to be realized.

Abstract: A virtual ground flash EEPROM array is based on a source-coupling, split-gate storage cell. The array includes a plurality of spaced-apart, parallel buried n+ bit lines formed in a P-type silicon substrate to define alternating source and drain lines that are segment-contacted. Field oxide islands formed in the array between adjacent source and drain lines define the substrate channel regions of the individual storage cell transistors. The poly1 floating gate of each cell is formed over a first portion of the substrate channel region and is separated from the channel region by a layer of floating gate oxide. Each floating gate includes a tunnelling arm that extends over the cell's source line and is separated therefrom by thin tunnel oxide. A poly2 word line is formed over the floating gates of the storage cells in each row of the array. The poly2 word line is separated from the underlying floating gate by a layer of oxide/nitride/oxide (ONO).

Abstract: A virtual ground flash EEPROM array is based on a source-coupling, split-gate storage cell. The array includes a plurality of spaced-apart, parallel buried n+ bit lines formed in a P-type silicon substrate to define alternating source and drain lines that are segment-contacted. Field oxide islands formed in the array between adjacent source and drain lines define the substrate channel regions of the individual storage cell transistors. The poly 1 floating gate of each cell is formed over a first portion of the substrate channel region and is separated from the channel region by a layer of floating gate oxide. Each floating gate includes a tunnelling arm that extends over the cell's source line and is separated therefrom by thin tunnel oxide. A poly2 word line is formed over the floating gates of the storage cells in each row of the array. The poly2 word line is separated from the underlying floating gate by a layer of oxide/nitride/oxide (ONO).

Abstract: An asymmetrical alternate metal virtual ground (AAMG) EPROM array utilizing an asymmetrical stacked gate cell with an N.sup.- source and four additional select lines is provided. The unintentional write problem associated with the conventional AMG EPROM array is eliminated by utilizing a high select transistor bias voltage and the asymmetrical cell. Soft write of the selected cell is minimized by biasing the source terminal during a read operation. Thus, bit line bias can be significantly increased to enhance the cell current and the memory performance without effecting data retention.

Abstract: The present invention provides a self-aligned trench isolation scheme for the MOS select transistors in an alternate metal virtual ground (AMG) EPROM array architecture. The new isolation scheme allows bit line to bit line spacing to be scaled to 0.6 .mu.m and below without compromising either data retention or memory performance characteristics. A new poly stack self-aligned etch scheme is also provided to scale the word line spacing to 0.6 .mu.m and below and, thus, allow a 64 Mbit EPROM array to be realized.