Abstract: A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.

Abstract: A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.

Abstract: A chiplet system with an auto-swapping function and a signal communication method thereof are provided. The chiplet system at least includes a first chiplet and a second chiplet. The signal communication method includes the following steps. The first chiplet and the second chiplet are electrified. The first chiplet and the second chiplet are reset and driven. Through a serial number information, the first chiplet and the second chiplet are identified. A handshaking communication procedure is executed by the first chiplet and the second chiplet to confirm whether a pin connection relationship between the first chiplet and the second chiplet is correct. If the pin connection relationship between the first chiplet and the second chiplet is incorrect, pin function switching is performed by the first chiplet or the second chiplet.

Abstract: A semiconductor device package has two integrated circuits. Each of the two integrated circuits has a core circuit and a digital input/output (I/O) interface circuit. The core circuits of the two integrated circuits are powered by two different core voltages, and the I/O circuits of the two integrated circuits are powered by the same core voltage selected from the two different core voltages.

Abstract: The present invention relates to a method for integrating an Ethernet switch system and a RTL design environment. The primary object of the present invention is to create a common communication channel between a system designer and an IC designer, more particularly to provide a converter program capable of converting a system verification means into a source of RTL verification, and the converter further having a function of self comparison, such that a fast and universal verification flow and database can be attained, and therefore a common consensus can be acquired between the system designer and the IC designer so as to reduce the product defects caused by designing. Moreover, an originally graphic user interface (GUI) is transformed into an ASCII character table to make the system designer and the IC designer have a good communication interface.

Abstract: An internal arbiter for a repeater in a computer network regulates access to a common communication channel through which the repeaters communicate with each other. The internal arbiter of the present invention uses a hybrid structure to detect possible contention between repeaters for access to the common communication channel. This hybrid structure combines the fast speed of a system which uses a plurality of dedicated wires (one for each repeater) to broadcast arbitration signals between repeaters, with expandability of a daisy chain interconnection to perform the same function. Additionally, the present invention provides a method for insuring that arbitration inputs are stabilized before they influence arbitration outputs by interposing a delay into the arbitration inputs, and only proceeding to generate arbitration outputs if the input values agree with the delayed input values.

Abstract: A 100BASE-T compliant integrated circuit multiport repeater provides one or more medium independent interfaces (MII's) and a plurality of physical interfaces. This facilitates connection of the repeater to one or more external medium access controller devices also implementing the MII standard. The multiport repeater device shares status, configuration and control management function of the MII among the plurality of physical ports. Therefore, only one MII physical address is needed for each multiport repeater, rather than for each physical transceiver in the system. The medium independent interfaces on the repeater chip share a number of pins and logic so that the total number of I/O pins required for a repeater chip according to the present invention with multiple medium independent interfaces is substantially reduced over a similar device which might have a plurality of independent medium independent interfaces.

Abstract: An apparatus for automatic configuration of multiple peripheral interface subsystems in a computer system, the computer system including a system expansion bus for adopting a plurality of functional peripheral interface subsystems, the apparatus comprises a software identification code buffer for buffering a software-generated identification code sent via the system expansion bus; a hardware identification code memory for storing a unique hardware identification code; a software identification code register for transmitting the software identification code via the system expansion bus for the access of the computer system; an instruction register for receiving instructions transmitted by the computer system; a hardware identification code detector for receiving the instruction transmitted by the computer system and stored in the instruction register to control the hardware identification code detector; and an automatic jump state circuit for receiving the instruction transmitted by the computer system and reg