Abstract: A semiconductor device includes a substrate, a plurality of first channel features, a plurality of second channel features, and an isolation structure. The first channel features are spacedly disposed over the substrate in a first direction normal to the substrate. The second channel features are spacedly disposed over the substrate in the first direction and are spaced apart from the first channel features in a second direction transverse to the first direction. The isolation structure is disposed between the first channel features and the second channel features in the second direction and has a convex top surface.

Abstract: A system for verifying chemotherapy medication preparation is disclosed, wherein the system includes: an image sensing module for capturing image information of a chemotherapy medication preparation process; an image recognition module that is in signal connection with the image sensing module and is configured to perform image recognition based on the image information and produce the corresponding identification result; and a computation and processing module that is in signal connection with the image recognition module and is configure to perform computation and comparison based on the identification result; to produce a verification result; to output feedback information when the verification result indicates a mismatch, in order for the image information to be recaptured and re-subjected to image recognition until the verification result indicates a match; and to output preparation process information when the verification result indicates a match.

Abstract: A method includes: forming first and second semiconductor fins; forming first and second gate structures over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming an n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, and having thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess, a sidewall of the p-type source/drain epitaxial structure being contiguous with a sidewall of the second dummy spacer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Abstract: A semiconductor structure includes a substrate, nanostructures, a dielectric layer, source/drain features, a gate structure, and inner spacers. The nanostructures are over the substrate and spaced apart from each other in a Z-direction. The dielectric layer is between and in contact with the nanostructures and the substrate in the Z-direction. The source/drain features are electrically connected to and on opposite sides of the nanostructures in an X-direction. The gate structure extends in a Y-direction and wraps around the nanostructures. The inner spacers are between the nanostructures and the substrate in the Z-direction. The inner spacers are on opposite sides of the dielectric layer in the X-direction.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Abstract: A method of forming a semiconductor structure, includes forming a fin structure over a substrate in a Z-direction; forming a dummy gate structure extending in a Y-direction and over the fin structure; and forming gate spacers on sidewalls of the dummy gate structure. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes removing a portion of the dummy gate structure to form a first trench that exposes upper portions of the gate spacers; forming an insulating material in the first trench; partially removing the insulating material to form insulating layers on sidewalls of the upper portions of the gate spacers; removing a remaining portion of the dummy gate structure to expose lower portions of the gate spacers; and partially etching the lower portions of the gate spacers.

Abstract: A semiconductor device structure is provided. The semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. A second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. A contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. The first electric wall has a gradually decreasing width W5 towards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.

Abstract: A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Abstract: A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.

Abstract: A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.

Abstract: A wireless network management method for a wireless network is provided. A length parameter of a slotframe is evaluated by considering an advertisement requirement and/or a data transmission requirement of the wireless network. The length parameter of the slotframe is adjusted to be relatively prime to a total number of available channels. At least one timeslot within the slotframe is assigned for matching the advertisement and/or the data transmission requirements, and the timeslot assignment of the slotframe is advertised.

Abstract: A wireless network management method for a wireless network is provided. A length parameter of a slotframe is evaluated by considering an advertisement requirement and/or a data transmission requirement of the wireless network. The length parameter of the slotframe is adjusted to be relatively prime to a total number of available channels. At least one timeslot within the slotframe is assigned for matching the advertisement and/or the data transmission requirements, and the timeslot assignment of the slotframe is advertised.

Abstract: A wireless network management method for a wireless network is provided. The wireless network management method includes: calculating a data transmission requirement of the wireless network; based on the calculated data transmission requirement, assigning at least an advertising timeslot in a slotframe; based on the calculated data transmission requirement, determining whether to assign and how to assign at least a data timeslot in the slotframe; and advertising a timeslot assignment of the slotframe.

Abstract: A raised floor includes a base plate, a raised plate, a support frame, and a transfer structure, in which the raised plate is parallelly disposed above the base plate; the support frame is disposed between the base plate and the raised plate; and the transfer structure that is configured with a first terminal and a second terminal is arranged by fixing the first terminal to the base plat and the second terminal to the raised plate.

Abstract: An adjustable weight lifting machine includes a bench board adjustably secured on a bench frame by adjustably engaging a locking bolt pivotally secured with the bench board with a corresponding pair of bolt holes formed in the bench frame adapted for a proper seating or sleeping by a trainee or user on the bench board, and a plurality of weights slidably held on two guiding rods having a pair of reinforcing ribs, each rib securing each rod to a supporting column of the machine having each weight formed with two side notches in two opposite side portions of the weight so as to be freely reciprocated on the guiding rods without being obstructed by the two reinforcing ribs secured on the rods.