Abstract: An anti-virus chip includes a first connection terminal, a second connection terminal, a detection unit and a processing unit. The first connection terminal and the second connection terminal are respectively coupled to a connection port and a system circuit of an electronic device. The detection unit detects whether the connection port is connected to an external device via the first connection terminal. When the detection unit detects that the connection port is connected to the external device, the processing unit performs a virus-scan program on the external device to determine whether a virus exists in the external device. When determining that a virus does not exist in the external device, the processing unit establishes a first transmission path between the first connection terminal and the second connection terminal. When determining that a virus exists in the external device, the processing unit does not establish the first transmission path.

Abstract: An anti-virus chip includes a first connection terminal, a second connection terminal, a detection unit and a processing unit. The first connection terminal and the second connection terminal are respectively coupled to a connection port and a system circuit of an electronic device. The detection unit detects whether the connection port is connected to an external device via the first connection terminal. When the detection unit detects that the connection port is connected to the external device, the processing unit performs a virus-scan program on the external device to determine whether a virus exists in the external device. When determining that a virus does not exist in the external device, the processing unit establishes a first transmission path between the first connection terminal and the second connection terminal. When determining that a virus exists in the external device, the processing unit does not establish the first transmission path.

Abstract: An integrated circuit (IC) is provided. The IC includes a molding compound, a plurality of pins, an exposed pad, a die surrounded by the molding compound, an adhesive material, and a plurality of bonding wires. The pins are disposed on at least one edge of the molding compound and separated from each other. The adhesive material is disposed between the die and the exposed pad and surrounded by the molding compound. The exposed pad is electrically connected to the die through one of the bonding wires, and the pins are electrically connected to the die through the remaining bonding wires. The die is configured to detect whether a chassis intrusion event is present in response to a signal from the exposed pad.

Abstract: An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.

Abstract: A charge control system includes a memory and a processing unit. The memory integrates a power consumption of the electronic device, a sleep signal, a boot signal, a hibernate signal or a shutdown signal received by the electronic device, a charge status of the charger, and a remaining power of the battery at the previous time point, as previous usage information. The processing unit creates an estimation model based on the previous usage information and an algorithm, to estimate an estimated power consumption of the electronic device, the estimated power of the battery and the charge probability of the charger corresponding to the current time point, the processing unit determines a target voltage based on the estimated power consumption, the estimated power, and the charge probability, the processing unit controls the charger to charge the battery, based on a current voltage and a target voltage.

Abstract: A serial bidirectional communication method is provided. The method includes: performing a downlink transmission and performing an uplink transmission. The downlink transmission includes: receiving first downlink data through a first transmission terminal, wherein the first downlink data comprises at least one control command, and the at least one control command is cascaded and configured to control at least one electronic device; removing one, corresponding to a local device, of the at least one control command from the first downlink data to form second downlink data, wherein the local device is one of the at least one electronic device; and when there is a control command remaining in the second downlink, outputting the second downlink data through a second transmission terminal. The uplink transmission includes outputting first uplink data through the first transmission terminal. The first uplink data includes local information generated by the local device.

Abstract: An anti-virus chip includes a first connection terminal, a second connection terminal, a detection unit and a processing unit. The first connection terminal and the second connection terminal are respectively coupled to a connection port and a system circuit of an electronic device. The detection unit detects whether the connection port is connected to an external device via the first connection terminal. When the detection unit detects that the connection port is connected to the external device, the processing unit performs a virus-scan program on the external device to determine whether a virus exists in the external device. When determining that a virus does not exist in the external device, the processing unit establishes a first transmission path between the first connection terminal and the second connection terminal. When determining that a virus exists in the external device, the processing unit does not establish the first transmission path.

Abstract: A serial bidirectional communication method is provided. The method includes: performing a downlink transmission and performing an uplink transmission. The downlink transmission includes: receiving first downlink data through a first transmission terminal, wherein the first downlink data comprises at least one control command, and the at least one control command is cascaded and configured to control at least one electronic device; removing one, corresponding to a local device, of the at least one control command from the first downlink data to form second downlink data, wherein the local device is one of the at least one electronic device; and when there is a control command remaining in the second downlink, outputting the second downlink data through a second transmission terminal. The uplink transmission includes outputting first uplink data through the first transmission terminal. The first uplink data includes local information generated by the local device.

Abstract: A bus system is provided. The bus system includes a master device, a bus and a plurality of slave devices. The slave devices and the master device are electrically connected through the bus. The master device communicates with the slave devices by using a one-to-one communication mechanism. The slave devices communicate with the master device by using an arbitration mechanism in which one of the slave devices is selected to communicate with the master device.

Abstract: A computer status diagnosis chip and a computer status diagnosis system including the same are provided. The chip is connected with the computer chip set and the first audio generator, and includes a receiving unit, an audio encoder and a driving unit. The receiving unit receives a detection signal from the computer chip set, and the audio encoder is connected to the receiving unit and encodes the detection signal as a first audio signal. The driving unit drives the first audio generator according to the first audio signal. By acoustic wave, the first audio generator transmits the first audio signal to a first audio receiver. Upon receipt of the first audio signal, an application program installed in the smart device is used to decode the first audio signal to obtain the detection signal, and a computer status is displayed on the smart device.

Abstract: A master electronic device used to perform communication with a slave electronic device is provided. The master electronic device includes a power module, an input and output (I/O) module, a processing module, a sample and hold module and a control module. The power module outputs power having a default operation voltage. The I/O module operates according to the power having the default operation voltage. The processing module controls the I/O module to generate and transmit a command signal to the slave electronic device. The sample and hold module receives and samples a response signal from the slave electronic device. The control module determines a slave operation voltage according to a high state voltage level of the response signal, so as to further control the power module to generate power having the slave operation voltage such that the I/O module operates accordingly.

Abstract: A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.

Abstract: A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.

Abstract: A fan driver system is provided, which includes a PWM generator, a DC generator, a control unit, a pull-down resistor and an integrator. The DC generator generates a DC test voltage, and a voltage of the pull-down resistor is detected to generate a determination signal. The PWM generator provides first and second PWM test signals having different duty cycles to the fan, respectively. The integrator integrates speed signal from the fan and corresponding to the first PWM test signal, to output a first integral signal, and integrates the speed signal corresponding to the second PWM test signal, to output a second integral signal. According to the first and second integral signals, and the determination signal, the control unit drives the PWM generator to selectively provide PWM working signal to the fan, and drive the DC generator to provide DC working voltage to the fan.

Abstract: A fan driver system is provided, which includes a PWM generator, a DC generator, a control unit, a pull-down resistor and an integrator. The DC generator generates a DC test voltage, and a voltage of the pull-down resistor is detected to generate a determination signal. The PWM generator provides first and second PWM test signals having different duty cycles to the fan, respectively. The integrator integrates speed signal from the fan and corresponding to the first PWM test signal, to output a first integral signal, and integrates the speed signal corresponding to the second PWM test signal, to output a second integral signal. According to the first and second integral signals, and the determination signal, the control unit drives the PWM generator to selectively provide PWM working signal to the fan, and drive the DC generator to provide DC working voltage to the fan.

Abstract: A bus system is provided. The bus system includes a master device, a bus and a plurality of slave devices. The slave devices and the master device are electrically connected through the bus. The master device communicates with the slave devices by using a one-to-one communication mechanism. The slave devices communicate with the master device by using an arbitration mechanism in which one of the slave devices is selected to communicate with the master device.

Abstract: A computer status diagnosis chip and a computer status diagnosis system including the same are provided. The chip is connected with the computer chip set and the first audio generator, and includes a receiving unit, an audio encoder and a driving unit. The receiving unit receives a detection signal from the computer chip set, and the audio encoder is connected to the receiving unit and encodes the detection signal as a first audio signal. The driving unit drives the first audio generator according to the first audio signal. By acoustic wave, the first audio generator transmits the first audio signal to a first audio receiver. Upon receipt of the first audio signal, an application program installed in the smart device is used to decode the first audio signal to obtain the detection signal, and a computer status is displayed on the smart device.

Abstract: A master electronic device used to perform communication with a slave electronic device is provided. The master electronic device includes a power module, an input and output (I/O) module, a processing module, a sample and hold module and a control module. The power module outputs power having a default operation voltage. The I/O module operates according to the power having the default operation voltage. The processing module controls the I/O module to generate and transmit a command signal to the slave electronic device. The sample and hold module receives and samples a response signal from the slave electronic device. The control module determines a slave operation voltage according to a high state voltage level of the response signal, so as to further control the power module to generate power having the slave operation voltage such that the I/O module operates accordingly.

Abstract: A voltage regulator with an on/off control on the control terminal of the power transistor of the voltage regulator. The power transistor of the voltage regulator drives the conversion from a first voltage to a second voltage. The voltage regulator provides a power-saving switch at the control terminal of the power transistor, and includes a power-saving control circuit controlling the power-saving switch. When the power-saving switch is turned on, the control signal for the power transistor is conveyed into the control terminal of the power transistor. When the power-saving switch is turned off, the connection between the control signal for the power transistor and the control terminal of the power transistor broken.

Abstract: A voltage regulator with an on/off control on the control terminal of the power transistor of the voltage regulator. The power transistor of the voltage regulator drives the conversion from a first voltage to a second voltage. The voltage regulator provides a power-saving switch at the control terminal of the power transistor, and includes a power-saving control circuit controlling the power-saving switch. When the power-saving switch is turned on, the control signal for the power transistor is conveyed into the control terminal of the power transistor. When the power-saving switch is turned off, the connection between the control signal for the power transistor and the control terminal of the power transistor broken.