Patents by Inventor Ming-Che Kao

Ming-Che Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6396090
    Abstract: A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: May 28, 2002
    Assignees: Industrial Technology Research Institute, General Semiconductor of Taiwan, Ltd.
    Inventors: Chih-Wei Hsu, Chung-Min Liu, Ming-Che Kao, Ming-Jinn Tsai, Pu-Ju Kung
  • Patent number: 6309929
    Abstract: A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: October 30, 2001
    Assignee: Industrial Technology Research Institute and Genetal Semiconductor of Taiwan, Ltd.
    Inventors: Chih-Wei Hsu, Chung-Min Liu, Ming-Che Kao, Ming-Jinn Tsai, Pu-Ju Kung