Patents by Inventor Ming-Cheng Lee
Ming-Cheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250116805Abstract: A key structure includes a light source and a light guiding assembly, a transparent cover, a semi-transparent and semi-reflective mirror, and a reflection mirror disposed above the light source. The light guiding assembly includes a center column and a platform surrounding the center column. A bottom surface of the center column faces the light source. The transparent cover is disposed on the light guiding assembly and covers the center column and the platform. An exterior side wall of the transparent cover has strip recesses surrounding the center column and the platform. The reflection mirror is disposed in the light guiding assembly. The reflection mirror and the semi-transparent and semi-reflective mirror face each other through the transparent cover. A part of light generated by the light source generates an infinity reflection between the strip recesses, the reflection mirror, and the semi-transparent and semi-reflective mirror after passing through the light guiding assembly.Type: ApplicationFiled: August 6, 2024Publication date: April 10, 2025Applicant: Acer IncorporatedInventors: Ching-Yi Lu, Ming-Cheng Wu, Yi-Heng Lee
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Publication number: 20250120197Abstract: A pixel sensor array may include a plurality of pixel sensors configured to generate color information associated with incident light, and a time of flight (ToF) sensor circuit configured to generate distance information associated with the incident light. The color information and the distance information may be used to generate a three-dimensional (3D) ToF color image. The ToF sensor circuit may be included under a DTI structure surrounding the plurality of pixel sensors in a top view of the pixel sensor array.Type: ApplicationFiled: October 5, 2023Publication date: April 10, 2025Inventors: Ming-Hsien YANG, Kun-Hui LIN, Chun-Hao CHOU, Kuo-Cheng LEE
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Patent number: 12271113Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.Type: GrantFiled: January 15, 2021Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Ming-Hui Weng, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Patent number: 12271017Abstract: A key structure includes a light source and a light guiding assembly, a transparent cover, a semi-transparent and semi-reflective mirror, and a reflection mirror disposed above the light source. The light guiding assembly includes a center column and a platform surrounding the center column. A bottom surface of the center column faces the light source. The transparent cover is disposed on the light guiding assembly and covers the center column and the platform. An exterior side wall of the transparent cover has strip recesses surrounding the center column and the platform. The reflection mirror is disposed in the light guiding assembly. The reflection mirror and the semi-transparent and semi-reflective mirror face each other through the transparent cover. A part of light generated by the light source generates an infinity reflection between the strip recesses, the reflection mirror, and the semi-transparent and semi-reflective mirror after passing through the light guiding assembly.Type: GrantFiled: August 6, 2024Date of Patent: April 8, 2025Assignee: Acer IncorporatedInventors: Ching-Yi Lu, Ming-Cheng Wu, Yi-Heng Lee
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Patent number: 12272554Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.Type: GrantFiled: July 27, 2023Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Lin Wei, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang
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Publication number: 20250098346Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.Type: ApplicationFiled: January 19, 2024Publication date: March 20, 2025Inventors: Wen-Chung Chen, Chia-Yu Wei, Kuo-Cheng Lee, Cheng-Hao Chiu, Hsiu Chi Yu, Hsun-Ying Huang, Ming-Hong Su
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Publication number: 20250087533Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.Type: ApplicationFiled: March 28, 2024Publication date: March 13, 2025Inventors: Ming-Hsing Tsai, Ya-Lien Lee, Chih-Han Tseng, Kuei-Wen Huang, Kuan-Hung Ho, Ming-Uei Hung, Chih-Cheng Kuo, Yi-An Lai, Wei-Ting Chen
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Patent number: 12243930Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.Type: GrantFiled: July 27, 2022Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Tai Chang, Tung-Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
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Publication number: 20250063833Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, wherein certain of the metal isolation features extend through the substrate to provide for full isolation between adjacent photodetectors and certain of the metal isolation features extend partially through the semiconductor layer to provide partially isolation between adjacent photodetectors.Type: ApplicationFiled: January 5, 2024Publication date: February 20, 2025Inventors: Ming-Hsien YANG, Kun-Hui LIN, Chun-Hao CHOU, Kuo-Cheng LEE
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Patent number: 12222643Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.Type: GrantFiled: October 22, 2022Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Cheng Liu, Ming-Hui Weng, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Patent number: 12218164Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.Type: GrantFiled: January 28, 2022Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Hsien Yang, Wen-I Hsu, Kuan-Fu Lu, Feng-Chi Hung, Jen-Cheng Liu, Dun-Nian Yaung, Chun-Hao Chou, Kuo-Cheng Lee
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Publication number: 20240170580Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.Type: ApplicationFiled: January 23, 2024Publication date: May 23, 2024Applicant: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Patent number: 11923460Abstract: A semiconductor structure includes several semiconductor stacks over a substrate, and each of the semiconductor stacks extends in a first direction, wherein adjacent semiconductor stacks are spaced apart from each other in a second direction, which is different from the first direction. Each of the semiconductor stacks includes channel layers above the substrate and a gate structure across the channel layers. The channel layers are spaced apart from each other in the third direction. The gate structure includes gate dielectric layers around the respective channel layers, and a gate electrode along sidewalls of the gate dielectric layers and a top surface of the uppermost gate dielectric layer. The space in the third direction between the two lowermost channel layers is greater than the space in the third direction between the two uppermost channel layers in the same semiconductor stack.Type: GrantFiled: June 28, 2022Date of Patent: March 5, 2024Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Patent number: 11916108Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: GrantFiled: January 30, 2023Date of Patent: February 27, 2024Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Publication number: 20240019491Abstract: A die-level electrical parameter extraction method includes: obtaining electrical parameters of a plurality of transistor types; obtaining measurement results of a plurality of logic blocks; estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks; and regarding a specific die of a wafer, obtaining die-level measurement of the plurality of logic blocks, and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results.Type: ApplicationFiled: June 7, 2023Publication date: January 18, 2024Applicant: MEDIATEK INC.Inventors: Jia-Horng Shieh, Po-Chao Tsao, Ming-Cheng Lee, Tung-Hsing Lee, Chi-Ming Lee, Yi-Ju Ting
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Patent number: 11744242Abstract: A living body specimen transport device for receiving multiple living body specimens has a frame, a rotating bracket, and a storage assembly. The rotating bracket can be rotated with respect to the frame. The storage assembly can receive a container with a living body specimen and be rotated with respect to the rotating bracket. A center of gravity of the storage assembly is lower than a pivoting point where the rotating bracket is mounted on the frame and a pivoting point where the storage assembly is mounted on the rotating bracket. With such structure, even when the living body specimen transport device is vibrated and shaken during transporting and then the frame of the living body specimen transport device is tilted or turned over, the rotating bracket and the storage assembly can rotate to be vertical by themselves, which keeps the living body specimen being soaked in the preservation solution.Type: GrantFiled: September 17, 2020Date of Patent: September 5, 2023Assignee: DRSIGNAL BIOTECHNOLOGY CO., LTD.Inventors: Hsin-Wu Mi, Ming-Cheng Lee, Jen-Sheng Hsu
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Publication number: 20230178607Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Applicant: Media Tek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Patent number: 11600700Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.Type: GrantFiled: October 28, 2021Date of Patent: March 7, 2023Assignee: MediaTek Inc.Inventors: Cheng-Tien Wan, Ming-Cheng Lee
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Publication number: 20230061138Abstract: A semiconductor device structure includes a semiconductor substrate, a first device formed in the first region of the semiconductor substrate and a second device formed in the second region of the semiconductor substrate. The first device includes a first gate structure on the semiconductor substrate. The first gate structure includes a first gate dielectric layer on the semiconductor substrate and a first gate layer on the first gate dielectric layer. The second device includes a second gate structure on the semiconductor substrate. The second gate structure includes a second gate dielectric layer on the semiconductor substrate and a second gate layer on the second gate dielectric layer. The first gate dielectric layer of the first device and the second gate dielectric layer of the second device have different dielectric material compositions.Type: ApplicationFiled: August 2, 2022Publication date: March 2, 2023Inventors: Yu-Lin YANG, Ming-Cheng LEE, Yuan-Fu CHUNG
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Patent number: D1062720Type: GrantFiled: April 9, 2020Date of Patent: February 18, 2025Assignee: Acer IncorporatedInventors: Ming-Cheng Wu, Yi-Heng Lee