Patents by Inventor Ming Cheng Liang

Ming Cheng Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117314
    Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Inventors: Ruei-Yue Liang, Chia-Hsin Lee, Kai-Ling Zhang, Po-Cheng Lin, Ming-Hsi Chuang, Yu-Chen Tsai, Peggy Leh Jiunn Wong
  • Publication number: 20240075071
    Abstract: Disclosed in the present invention is an optimized cell transplant. The optimized cell transplant is formed by performing gene induction and modification on a mesenchymal stem cell in the form of a small molecule and protein composition. The expression levels of CD200 gene, Galectin-9 gene and VISTA gene can be increased synchronously after cell culture. Vector virus infection and plasmid transfection are not required in the cell preparation process, so that high biological safety and great clinical application value of cells are achieved.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 7, 2024
    Inventors: Ruei-Yue Liang, Kai-Ling Zhang, Ming-Hsi Chuang, Po-Cheng Lin, Peggy Leh Jiunn Wong, Chia-Hsin Lee
  • Patent number: 9093179
    Abstract: A method for improving test coverage of pads of a chip, where the chip includes a control unit, a plurality of pads, and a storage unit, and the storage unit includes a plurality of blocks, includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 28, 2015
    Assignee: Etron Technology, Inc.
    Inventors: Shih-Hsing Wang, Ming-Cheng Liang, Kuo-Cheng Ting
  • Publication number: 20140075251
    Abstract: A method capable of improving test coverage of chip pads, where the chip includes a control unit, a plurality of pads, and a storage unit, is disclosed. The storage unit includes a plurality of blocks. The method includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed.
    Type: Application
    Filed: April 18, 2013
    Publication date: March 13, 2014
    Applicant: Etron Technology, Inc.
    Inventors: Shih-Hsing Wang, Ming-Cheng Liang, Kuo-Cheng Ting
  • Patent number: 7940588
    Abstract: The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: May 10, 2011
    Assignee: Etron Technology, Inc.
    Inventors: Der-Min Yuan, Ming-Cheng Liang, Kuo-Hua Lee
  • Publication number: 20100171509
    Abstract: The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.
    Type: Application
    Filed: August 27, 2009
    Publication date: July 8, 2010
    Inventors: Der-Min YUAN, Ming-Cheng Liang, Kuo-Hua Lee
  • Patent number: 6462712
    Abstract: A patch antenna device includes an antenna patch, and one or more capacitors loaded into the antenna patch for increasing an equivalent working area to the antenna patch. The capacitor may be any suitable capacitor, such as the chip capacitor. The provision of the capacitor into the antenna patch allows the electricity to flow into and to flow out of the capacitor, and consumes less electric power. A ground board and a dielectric plate are attached to the antenna patch. One or more feeds and probes are loaded into the antenna patch for exciting various modes.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: October 8, 2002
    Inventor: Ming Cheng Liang