Abstract: A contact lens includes a first optical region, a second optical region, and a transition region. The first optical region is shaped to form a first power profile. The second optical region is shaped to form a second power profile. The transition region is joined between the first optical region and the second optical region and is shaped to form a third power profile with a power variation radially changing from the first power profile to the second power profile as a radius increasing. The transition region includes a first subzone, a second subzone and a third subzone. Each of the first subzone and the third subzone has a gradual power variation measured from a lens center to a lens edge as compared to the second subzone, and the second subzone has a steep power variation measured from the lens center to the lens edge.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.

Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: Disclosed example reusable holding components include: a frame with a fastener receiving opening surrounding by a fastener guiding wall and extending from a first surface of the frame to a second surface of the frame; at least two pins located on opposite sides of the fastener receiving opening; each of the pins having a first end disposed on the second surface of the frame, each pin extending away from the second surface to a second end of each pin, wherein the second end of each pin includes at least two elongated segments with hooks disposed on a head portion of each of the at least two elongated segments; and a heatsink having a top surface and opposite bottom surface and the top surface connected to the reusable holding component by the at least one pin.

Abstract: A reusable holding component is provided. The reusable holding component may comprise a frame with a fastener receiving opening extending from a first surface of the frame to a second surface of the frame, and at least one pin disposed on and extending away from the second surface of the frame, wherein the at least one pin includes at least two elongated segments with hooks disposed on a head portion of each of the at least two elongated segments. A heat transfer device and an electronic device with a heatsink are also provided.

Abstract: A reusable holding component is provided. The reusable holding component may comprise a frame with a fastener receiving opening extending from a first surface of the frame to a second surface of the frame, and at least two pins disposed on and extending away from the second surface of the frame, wherein each of the at least two pins includes a head portion, at least one elongated segment connected to a portion of the head portion, and a hook disposed on the at least one elongated segment. A heat transfer device and an electronic device with a heatsink are also provided.

Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A universal switching platform is configured to test a device under test, and includes a first power source, a first switch, a second switch and a second power source. The first switch, the second switch and the second power source are coupled in series between positive and negative terminals of the first power source. The common node of the first and second switches and the negative terminal of the first power source are configured to be respectively coupled to first and second terminals of the device under test. The universal switching platform provides a voltage and a current to test the device under test when the first and second switches are controlled to transition between conduction and non-conduction.

Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Abstract: A level adjusting circuit includes a parallel resistor-capacitor (RC) sub-circuit, a first diode and an adjustable voltage supply. The RC sub-circuit includes an input capacitor and an input resistor, and includes an input node electrically connected to a driving signal source for receiving a driving signal therefrom, and an output node that outputs an adjusted driving signal. The first diode and the adjustable voltage supply are electrically connected, and are further electrically connected to the output node and a reference voltage node, respectively.

Abstract: A gate-driving circuit includes a unidirectional module and two driving modules, and has a low-potential terminal, an output terminal, and two input terminals via which two driving signals are received. Each of the driving modules includes a capacitor and a resistor that are connected in parallel and between the output terminal and the respective one of input terminals, a power source that is connected between the output terminal and the low-potential terminal, and a diode that is connected between the output terminal and the power source. The unidirectional module is connected between the output terminal and one of the driving modules, and allows an electrical signal to pass only from the one of the driving modules to the output terminal.

Abstract: A projection device having an information input unit, a storage unit, a scaling unit, an image processing unit and a projection unit is provided. The information input unit receives the image file corresponded to a compressed personalized startup image file. The storage unit has a first storage block storing a preset startup image file and a second storage block. The scaling unit generates a projected image signal according to the compressed personalized startup image file, and the scaling unit stores the compressed personalized startup image file in the at least one second storage block. The image processing unit generates a projection control signal according to the projected image signal. The projection unit generates an image beam according to the projection control signal, and projects the image beam on a projection surface to form the startup image screen. The disclosure further provides a personalized startup image setting method.

Abstract: A gate-driving circuit includes a unidirectional module and two driving modules, and has a low-potential terminal, an output terminal, and two input terminals via which two driving signals are received. Each of the driving modules includes a capacitor and a resistor that are connected in parallel and between the output terminal and the respective one of input terminals, a power source that is connected between the output terminal and the low-potential terminal, and a diode that is connected between the output terminal and the power source. The unidirectional module is connected between the output terminal and one of the driving modules, and allows an electrical signal to pass only from the one of the driving modules to the output terminal.

Abstract: A level adjusting circuit includes a parallel resistor-capacitor (RC) sub-circuit, a first diode and an adjustable voltage supply. The RC sub-circuit includes an input capacitor and an input resistor, and includes an input node electrically connected to a driving signal source for receiving a driving signal therefrom, and an output node that outputs an adjusted driving signal. The first diode and the adjustable voltage supply are electrically connected, and are further electrically connected to the output node and a reference voltage node, respectively.

Abstract: A universal switching platform is configured to test a device under test, and includes a first power source, a first switch, a second switch and a second power source. The first switch, the second switch and the second power source are coupled in series between positive and negative terminals of the first power source. The common node of the first and second switches and the negative terminal of the first power source are configured to be respectively coupled to first and second terminals of the device under test. The universal switching platform provides a voltage and a current to test the device under test when the first and second switches are controlled to transition between conduction and non-conduction.

Abstract: A frame assembly is adapted to fix at least a film, an outer edge of the film is provided with at least a first assembly portion, and the frame assembly comprises a back plate, a frame unit, and at least a fixing unit. The frame unit includes an outer frame portion disposed outside an outer edge of the back plate, and a holding portion connected to the outer frame portion, wherein the holding portion has a bottom surface and a top surface opposite to the bottom surface. The fixing unit is combined with the bottom surface of the holding portion, and the fixing unit includes a second assembly portion that is not covered by the holding portion and combined with the first assembly portion of the film, so that the film is fixed in the frame assembly.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.