Abstract: A stable manufacturing efficiency generating method includes the steps: generating a real-time grouping parameter set according to a plurality of historical efficiency values; grouping a plurality of real-time efficiency values corresponding to a product to generate a plurality of real-time efficiency groups according to the real-time grouping parameter set; selecting one of the real-time efficiency groups having most real-time efficiency values as a stable efficiency group; and generating a stable manufacturing efficiency value according to an average value of the real-time efficiency values in the stable efficiency group.

Abstract: A production performance management device and a production performance management method thereof are provided. The production performance management device includes a connection interface, a storage and a processor. The connection interface receives production data. The storage stores the production data and a production performance management program. The processor runs the production performance management program. The production performance management program defines a main objective, a plurality of measurement indices, a plurality of factors, a custom mapping function between the main objective and the measurement indices and a plurality of specific mapping functions between the measurement indices and the factors, and uses the custom mapping function and the specific mapping functions to decide a factor value of each of the factors from the production data to make a main objective value of the main objective meet a main constraint.

Abstract: A method of processing application security for uses in a platform-as-a-service layer (PAAS layer) includes steps as follows. First, an application program is scanned to find out a vulnerable code segment. Then, when the vulnerable code segment isn't fixed through a security process, a secure code segment is weaved into this unfixed vulnerable code segment, so as to ensure the security of the application program. Moreover, a system of processing application security is also disclosed in specification.

Abstract: In a multiprocessor system, memory accesses by the individual processing elements are checked by a common controller. The controller includes a table of values defining valid memory locations for a task. The controller verifies the address value used by each instruction to ensure that, it is within a valid memory area for the particular task. Additional circuitry for the controller and processing elements allows finer control, of memory accessibility. The multiprocessor system may be coupled to a host computer through a buffer. Data is serially written into the buffer by the host and is read out of the buffer in parallel by the multiprocessor system. The buffer used in this system includes apparatus which calculates an error correction code from a serial data stream and passes this code, along with the data, to the multiprocessor system. The multiprocessor system includes apparatus which processes the data in parallel to handle errors occurring during transfers as indicated by the code.

Abstract: A two-dimensional input/output system for a massively parallel SIMD computer system providing an interface for the two-way transfer of data between a host computer and the SIMD computer. A plurality of buffers equal in number, and distributed with the individual processing elements of the SIMD computer are used to provide a temporary storage area which allows data in different formats to be mapped in a format suitable for transfer to the host computer or for transfer to the SIMD processing elements. The temporary storage is controlled in such a way as to transfer entire blocks of data in a single SIMD system clock cycle thereby achieving an input/output data rate of N bits/cycle for a SIMD computer consisting of N processors. The system is capable of handling irregular as well as regular data structures. The system also emphasizes a distributed approach in having the input/output system divided into N pieces and distributed to each processor to reduce the wiring complexity while maintaining the I/O rate.