Abstract: A method for fabricating integrated circuits comprises: forming, on a frontside of a substrate, a plurality of active components of an integrated circuit; forming, on the frontside of the substrate, a plurality of dummy components each laterally disposed next to one or more of the active components; forming a plurality of first via structures vertically extending through the substate from its backside to the frontside; forming a second via structure vertically extending through the substate from the backside to the frontside; and forming, on the backside of the substrate, a second interconnect structure.

Abstract: A semiconductor device includes a digital section, an analog active section, and an analog guard ring section between the analog active section and the digital section. The semiconductor device includes M_1st segments. The M_1st segments include a first M_1st segment extending in a first direction; and a second M_1st segment extending in the first direction, wherein the second M_1st segment is collinear with the first M_1st segment, and a first gap is between the first M_1st segment and the second M_1st segment. The semiconductor device includes active regions in a substrate. The active regions include first and second active regions extending in the first direction, the first active region being adjacent to the second active region, and the first and second active regions are separated by a second gap greater than or equal to the first gap.

Abstract: Methods of designing integrated circuits incorporating an analog ECO flow are provided. An example method comprises receiving an initial design and performing an auto-marker process. The auto-marker process comprises performing a first auto-marker process to surround a first plurality of active cells of the design with first computer-aided design (CAD) layers corresponding to a first plurality of engineering change order (ECO) cells, performing an enhanced auto-marker process to cover irregular shapes of the design with second CAD layers corresponding to a second plurality of ECO cells, and performing a second auto-marker process to fill empty areas of the design with third CAD layers corresponding to a third plurality of ECO cells. The method further includes filling the design with the first plurality of ECO cells, the second plurality of ECO cells, and the third plurality of ECO cells.

Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

Abstract: One aspect of the present disclosure pertains to a semiconductor structure. The semiconductor structure includes first and second active regions extending lengthwise along a first direction and metal gate structures extending lengthwise along a second direction over channels of the first and second active regions. The semiconductor structure includes an insulating structure cutting through the metal gate structures. The insulating structure is disposed between the first and the second active regions along the second direction. The semiconductor structure includes source/drain (S/D) contacts over the insulating structure and over S/D features of the first and second active regions. The S/D contacts extend lengthwise along the second direction. And the semiconductor structure includes a feedthrough via contacting a bottom surface of the S/D contacts and penetrating through a portion of the insulating structure.

Abstract: A semiconductor device includes: first and second active regions (ARs) included correspondingly in abutting first and second analog cell regions, a region where the first and second analog cell regions abut (analog-cell-boundary (ACB) region) extending from about a top boundary of the first AR to about a bottom boundary of the second AR; via-to-PGBM_1st-segment contact structures (VBs) correspondingly being under the first or second ARs, a long axis of each VB and a short axis of each of the first and second ARs having about a same length; and a PG segment in a first buried metallization layer (PGBM_1st segment) under the VBs, the PGBM_1st segment underlapping a majority of each of the VBs, and a Y-midline of the PGBM_1st segment being at or proximal to where the first and second analog cell regions abut and thus being at or proximal to a middle of the ACB region.

Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.