Abstract: A Schottky diode and a manufacturing method thereof are provided. The Schottky diode comprises a substrate, a first conductive type epitaxial layer, a plurality of trench structures, a plurality of second conductive type heavily-doped barrier regions and a plurality of second conductive type doped regions. The first conductive type epitaxial layer is disposed on the substrate, and a plurality of trench structures are disposed in the first conductive type epitaxial layer. Each of the second conductivity type heavily-doped barrier regions are correspondingly disposed at the bottom of each trench structure, and each of the second conductivity type doping regions are correspondingly disposed on the side walls of each trench structure, so that a plurality of super junctions are formed between each second conductivity type doped region and the first conductivity type epitaxial layer between each trench structure.

Abstract: A transistor device and a manufacturing method thereof are provided. The transistor device includes: a substrate, a first conductive type epitaxial layer, a second conductive type body region, a second conductive type heavily doped recess, and two self-aligned first conductive type heavily doped regions. The first conductive type epitaxial layer is disposed on the substrate, the second conductive type body region is disposed on the first conductive type epitaxial layer, and the second conductive type heavily doped recess is disposed on the second conductive type body region. The two self-aligned first conductive type heavily doped regions are self-aligned and disposed on the upper edges of both sides of the second conductive type heavily doped recess.

Abstract: A transistor device and a manufacturing method thereof are provided. The transistor device includes a silicon carbide substrate, a silicon carbide epitaxial layer, a first conductive type doped body region, a second conductive type heavily doped region, a source trench and a first conductive type ion doped interface. The silicon carbide epitaxial layer is disposed on the silicon carbide substrate. The first conductive type doped body region is disposed on the silicon carbide epitaxial layer, the second conductive type heavily doped region is disposed in the first conductive type doped body region, the source trench is disposed in the silicon carbide epitaxial layer and is adjacent to the second conductive type heavily doped region and the first conductive type doped body region, and the first conductive ion doped interface is disposed to surround the sidewall of the source trench.

Abstract: A transistor device and a manufacturing method thereof are provided. The manufacturing method for a transistor device includes the following steps: first, providing a first conductive type epitaxial layer disposed on a substrate. Second, a first photomask is used to implant a second conductive type ion into the first conductive type epitaxial layer to form a second conductive type body region. Then, a first conductive type ion implantation is performed on the second conductive type body region using a second photomask to form a first conductive type heavily doped region in the second conductive type body region. Finally, a second conductive type tilt ion implantation is performed on the second conductive type body region on both sides of the first conductive type heavily doped region using the second photomask to form two in-situ self-aligned second conductive type doped channels in the second conductive type body region on both sides of the first conductive type heavily doped region.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a transistor and a snubber circuit. The transistor and the snubber circuit are disposed on the same substrate, and are electrically connected. The snubber circuit has a polycrystalline silicon layer and a dielectric layer, which are adjacently arranged and electrically connected in series. The polycrystalline silicon layer is electrically connected to a source of the transistor, and the dielectric layer is electrically connected to a drain of the transistor so that the polycrystalline silicon layer acts as a resistor, the dielectric layer acts as a capacitor and the snubber circuit acts as an RC snubber circuit.

Abstract: The disclosure provides an eye state assessment method and an electronic device. The method includes: obtaining an optic disc image area from a first fundus photography and generating multiple optic cup-to-disc ratio assessment results by multiple first models based on the optic disc image area; obtaining a first assessment result of an eye based on the optic cup-to-disc ratio assessment results; performing multiple data augmentation operations on the first fundus photography to generate multiple second fundus photographies; generating multiple retinal nerve fiber layer (RNFL) defect assessment results by multiple second models based on the second fundus photographies; obtaining a second assessment result of the eye based on the RNFL defect assessment results; and obtaining an optic nerve assessment result of the eye based on the first assessment result and the second assessment result.

Abstract: The disclosure provides an eye state assessment method and an electronic device. The method includes: obtaining an optic disc image area from a first fundus photography and generating multiple optic cup-to-disc ratio assessment results by multiple first models based on the optic disc image area; obtaining a first assessment result of an eye based on the optic cup-to-disc ratio assessment results; performing multiple data augmentation operations on the first fundus photography to generate multiple second fundus photographies; generating multiple retinal nerve fiber layer (RNFL) defect assessment results by multiple second models based on the second fundus photographies; obtaining a second assessment result of the eye based on the RNFL defect assessment results; and obtaining an optic nerve assessment result of the eye based on the first assessment result and the second assessment result.

Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.

Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.