Patents by Inventor Ming-Chia Yang

Ming-Chia Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230060825
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Chen-Yui Yang, Ke-Chia Tseng, Hsien-Chung Huang, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20230062257
    Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsuan Chen, Ming-Chia Tai, Yu-Hsien Lin, Shun-Hui Yang, Ryan Chia-Jen Chen
  • Publication number: 20230063251
    Abstract: A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling Liao, Ming-Chih Yew, Che-Chia Yang, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11569084
    Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Yu Lin, Chih-Chiang Chang, Chien-Hung Chen, Ming-Hua Yu, Tsung-Hsi Yang, Ting-Yi Huang, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20220406730
    Abstract: A package structure is provided. The package structure includes a redistribution structure and a semiconductor die over the redistribution structure, and bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The bonding elements include a first row of bonding elements and a second row of bonding elements. In a plan view, the second row of bonding elements is arranged between the first row of bonding elements and an extending line of the second sidewall. A minimum distance between the second row of bonding elements and the first sidewall is greater than the minimum distance between the first row of bonding elements and the first sidewall.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Po-Chen LAI, Chin-Hua WANG, Ming-Chih YEW, Che-Chia YANG, Shu-Shen YEH, Po-Yao LIN, Shin-Puu JENG
  • Patent number: 11529435
    Abstract: The present disclosure provides a method for manufacturing a porous film, including: preparing a polymer mixture solution, wherein the polymer mixture solution includes polycaprolactone and at least one hydrophobic polymer; adding solid particles as a dispersing agent to the polymer mixture solution and mixing the solid particles with the polymer mixture solution, wherein the amount of solid particles added is enough to convert the polymer mixture solution into a solid mixture; drying the solid mixture to form a film; and washing the film with a washing fluid to remove the solid particles from the film to form the porous film, wherein the weight ratio of the polycaprolactone to the at least one hydrophobic polymer is about 1:0.1-10, and wherein the weight ratio of the polycaprolactone and the at least one hydrophobic polymer to the solid particles is about 1:0.01-250.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: December 20, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Ming-Chia Yang, Chia-Chi Ho, Fang-Jie Jang, Che-Yu Ou, Chi-Hsiang Liao, Brian Hsu, Tai-Horng Young
  • Publication number: 20220388293
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer, and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution is 1:0.01-1. Moreover, the second polymer solution is composed of a second hydrophilic solution.
    Type: Application
    Filed: August 11, 2022
    Publication date: December 8, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Yu-Chi WANG, Ming-Chia YANG, Yu-Bing LIOU, Wei-Hong CHANG, Yun-Han LIN, Hsin-Yi HSU, Yun-Chung TENG, Chia-Jung LU, Yi-Hsuan LEE, Jian-Wei LIN, Kun-Mao KUO, Ching-Mei CHEN
  • Publication number: 20220384390
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 1, 2022
    Inventors: Che-Chia YANG, Shu-Shen YEH, Po-Chen LAI, Ming-Chih YEW, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20220384437
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
  • Publication number: 20220367314
    Abstract: A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Shu-Shen YEH, Che-Chia YANG, Chia-Kuei HSU, Ming-Chih YEW, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20220367382
    Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a first surface of the substrate. The ring structure is located over the first surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the first surface of the substrate and a top surface opposite the bottom surface. The ring structure includes a plurality of side parts and a plurality of corner parts recessed from the top surface and thinner than the side parts. Any two of the corner parts are separated from one another by one of the side parts. The adhesive layer is interposed between the bottom surface of the ring structure and the first surface of the substrate.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 17, 2022
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chia-Kuei Hsu, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11458715
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer; and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution is 1:0.01-1. Moreover, the second polymer solution consists of a second hydrophilic solution.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: October 4, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Yu-Chi Wang, Ming-Chia Yang, Yu-Bing Liou, Wei-Hong Chang, Yun-Han Lin, Hsin-Yi Hsu, Yun-Chung Teng, Chia-Jung Lu, Yi-Hsuan Lee, Jian-Wei Lin, Kun-Mao Kuo, Ching-Mei Chen
  • Publication number: 20220293415
    Abstract: A method for removing nodule defects is disclosed. The nodule defects may be formed on a non-selected portion of a semiconductor structure during formation of a semiconductor region on a selected portion of the semiconductor structure. A plasma having a higher selectivity to etch the nodule defects relative to the semiconductor region may be used to selectively remove the nodule defects on the non-selected portion.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Yu LIN, Chih-Chiang CHANG, Chien-Hung CHEN, Ming-Hua YU, Tsung-Hsi YANG, Ting-Yi HUANG, Chii-Horng LI, Yee-Chia YEO
  • Patent number: 11401441
    Abstract: Provided are Chemical Mechanical Planarization (CMP) formulations that offer high and tunable Cu removal rates and low copper dishing for the broad or advanced node copper or Through Silica Via (TSV). The CMP compositions provide high selectivity of Cu film vs. other barrier layers, such as Ta, TaN, Ti, and TiN, and dielectric films, such as TEOS, low-k, and ultra low-k films. The CMP polishing formulations comprise solvent, abrasive, at least three chelators selected from the group consisting of amino acids, amino acid derivatives, organic amine, and combinations therefor; wherein at least one chelator is an amino acid or an amino acid derivative. Additionally, organic quaternary ammonium salt, corrosion inhibitor, oxidizer, pH adjustor and biocide are used in the formulations.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 2, 2022
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Xiaobo Shi, Laura M. Matz, Chris Keh-Yeuan Li, Ming-Shih Tsai, Pao-Chia Pan, Chad Chang-Tse Hsieh, Rung-Je Yang, Blake J. Lew, Mark Leonard O'Neill, Agnes Derecskei
  • Publication number: 20220209023
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
  • Publication number: 20220169808
    Abstract: An anti-curling film is provided. The anti-curling film includes a first portion and a second portion covering the first portion. The first portion includes polylactic acid (PLA), polycaprolactone (PCL), polyethylene glycol dimethacrylate (PEGDMA) and a photoinitiator. The second portion includes polycaprolactone (PCL), gelatin, hyaluronic acid (HA), alginate (AA), polyvinyl alcohol (PVA) or a combination thereof.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 2, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Hong CHANG, Ching-Mei CHEN, Grace H. CHEN, Hsin-Hsin SHEN, Yuchi WANG, Ming-Chia YANG, Li-Hsin LIN, Sen-Lu CHEN, Yi-Hsuan LEE, Jian-Wei LIN, Liang-Cheng SU
  • Patent number: 11298147
    Abstract: A minimally invasive surgical device includes a main body, a buffer assembly and a cutter bit. The main body includes an inner tube and an outer tube, wherein the inner tube is disposed in the outer tube. An end of the buffer assembly is connected to the inner tube. The cutter bit is connected to another end of the buffer assembly, wherein the cutter bit has a cutting portion. When the cutting portion is in contact with an object, the buffer assembly is adapted to enable the cutter bit to move relatively to the inner tube to decrease a cutting force between the cutting portion and the object, and is adapted to enable the cutting portion to be tilted with a surface of the object.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 12, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Chuan Jiang, Hsin-Hsin Shen, Ming-Chia Yang, Yun-Han Lin, Wei-Hong Chang
  • Patent number: 11154637
    Abstract: A biodegradable sealant includes: a polyethylene glycol derivative; a photoinitiator; and a solvent, wherein the content of the polyethylene glycol derivative is about 10-75 wt % in the biodegradable sealant. The polyethylene glycol derivative is obtained by a substitution reaction, and in the substitution reaction, the polyethylene glycol is modified with methacrylic anhydride.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: October 26, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Yu-Chi Wang, Sen-Lu Chen, Yu-Bing Liou, Jian-Wei Lin, Yi-Hsuan Lee, Ming-Chia Yang, Ying-Wen Shen, Wei-Lin Yu
  • Publication number: 20210322625
    Abstract: The present disclosure provides a method for manufacturing a porous film, including: preparing a polymer mixture solution, wherein the polymer mixture solution includes polycaprolactone and at least one hydrophobic polymer; adding solid particles as a dispersing agent to the polymer mixture solution and mixing the solid particles with the polymer mixture solution, wherein the amount of solid particles added is enough to convert the polymer mixture solution into a solid mixture; drying the solid mixture to form a film; and washing the film with a washing fluid to remove the solid particles from the film to form the porous film, wherein the weight ratio of the polycaprolactone to the at least one hydrophobic polymer is about 1:0.1-10, and wherein the weight ratio of the polycaprolactone and the at least one hydrophobic polymer to the solid particles is about 1:0.01-250.
    Type: Application
    Filed: May 5, 2021
    Publication date: October 21, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin SHEN, Ming-Chia YANG, Chia-Chi HO, Fang-Jie JANG, Che-Yu OU, Chi-Hsiang LIAO, Brian HSU, Tai-Horng YOUNG
  • Publication number: 20210196648
    Abstract: A drug-containing multilayer film provided. The drug-containing multilayer film includes: a drug-containing layer; and an anti-adhesion layer on a surface of the drug-containing layer. The drug-containing layer is composed of a first composition including a first polymer material and a drug, and the first polymer material includes at least one selected from the group consisting of: polylactic acid (PLA) and polyethylene glycol (PEG), and the weight ratio of the first polymer material to the drug is about 1:0.01-0.3. The anti-adhesion layer is composed of a second composition, and the second composition includes a second polymer material, and the second polymer material includes at least one selected from the group consisting of polylactic acid and polyethylene glycol.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Yuchi WANG, Li-Hsin LIN, Ming-Chia YANG, Hsiu-Hua HUANG, Liang-Cheng SU, Ying-Hsueh CHAO, Jing-En HUANG