Patents by Inventor Ming-Chieh Hsu

Ming-Chieh Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515256
    Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin Chiu, Ming-Hsien Lin, Chia-Tung Hsu, Lun-Chieh Chiu
  • Publication number: 20220367377
    Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin CHIU, Ming-Hsien LIN, Chia-Tung HSU, Lun-Chieh CHIU
  • Publication number: 20220367200
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Application
    Filed: June 20, 2022
    Publication date: November 17, 2022
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20220335192
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Inventors: Chia-Ping CHIANG, Ming-Hui CHIH, Chih-Wei HSU, Ping-Chieh WU, Ya-Ting CHANG, Tsung-Yu WANG, Wen-Li CHENG, Hui En YIN, Wen-Chun HUANG, Ru-Gun LIU, Tsai-Sheng GAU
  • Patent number: 11454243
    Abstract: A data processing method is proposed, including: sensing, via at least one sensing portion, target information of a target device; receiving and processing, via an electronic device, the target information of the sensing portion to form feature information; processing, via the electronic device, the feature information into a label matrix, and establishing, via an artificial intelligence training method, a target model based on the label matrix; and after the electronic device captures real-time information of the target device, predicting, via the target model, a life limit of the target device, wherein a content of the target information is corresponding to a content of the real-time information. Thus, a good target model is constituted and is advantageous in training artificial intelligence by processing the feature information into the label matrix.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 27, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Hsiang Hsu, Chun-Chieh Wang, Hung-Tsai Wu
  • Publication number: 20220262926
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 18, 2022
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20220238454
    Abstract: A semiconductor structure includes a multi-level interconnect structure, a passivation layer, a barrier layer, and a pad layer. The passivation layer is above the multi-level interconnect structure. The barrier layer lines an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure. The barrier layer includes a first layer, a second layer, a third layer, and a fourth layer. The first layer is in a nano-crystalline phase. The second layer is above the first layer and in an amorphous phase. The third layer is above the second layer and in a polycrystalline phase. The fourth layer is above the third layer and in a nano-crystalline phase. The pad layer is above the barrier layer.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin CHIU, Ming-Hsien LIN, Chia-Tung HSU, Lun-Chieh CHIU
  • Patent number: 11392742
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 11387109
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu, deseased
  • Publication number: 20220206336
    Abstract: An electronic device is provided. The electronic device includes a backlight module, a display panel, an adhesive layer, and a flexible circuit board. The display panel is disposed on the backlight module. The adhesive layer is disposed between the backlight module and the display panel. The adhesive layer includes an opening. The flexible circuit board is electrically connected to the display panel. The flexible circuit board overlaps the opening.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 30, 2022
    Inventors: Shan-Shan HSU, Ming-Tsang WU, Chia-Chieh FAN
  • Publication number: 20220209146
    Abstract: A flexible display module includes a first light-transmissive layer and a first display layer. The first light-transmissive layer includes a display surface. The first light-transmissive layer has a first width in a second direction. The first display layer is disposed below the first light-transmissive layer. The first display layer has a second width in the second direction. The first display layer includes a circuit layer. The flexible display module is configured to be bent along an axis, the axis extends along a first direction, the first direction is perpendicular to the second direction, and the first width is greater than the second width. A line width of the circuit layer more close to a periphery of the display surface is less than a line width of the circuit layer more close to an inner area of the display surface.
    Type: Application
    Filed: November 4, 2021
    Publication date: June 30, 2022
    Inventors: Ming-Chang HSU, Chih-Chieh LIN, Ming-Hsuan YU, Ming-Wei LIN
  • Publication number: 20210375645
    Abstract: A chemical dispensing system is capable of simultaneously supplying a semiconductor processing chemical for production and testing through the use of independent chemical supply lines, which reduces production downtime of an associated semiconductor process, increases throughput and capability of the semiconductor process, and/or the like. Moreover, the capability to simultaneously supply the semiconductor processing chemical for production and testing allows for an increased quantity of semiconductor processing chemical batches to be tested with minimal impact to production, which increases quality control over the semiconductor processing chemical. In addition, the independent chemical supply lines may be used to supply the semiconductor processing chemical to production while independently filtering semiconductor processing chemical directly from a storage drum through a filtration loop.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Ming-Chieh HSU, Yung-Long CHEN, Fang-Pin CHIANG, Feng-An YANG, Ching-Jung HSU, Chi-Tung LAI
  • Patent number: 11121159
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20200020729
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10468443
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20190123085
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10177186
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20170110119
    Abstract: An electronic interactive chanting and praying system device includes a substrate, a voice input device installed to the substrate for receiving a voice message, a control processing device installed to the substrate and coupled to the voice input device for receiving the voice message and conducting a voice recognition processing to selectively generate a light source control instruction and a sound source control instruction, a light emitting device installed to the substrate and coupled to the control processing device for executing a light emitting mode according to the light source control instruction, and a speaker installed to the substrate and coupled to the control processing device for playing a piece of religious voice information according to the sound source control instruction.
    Type: Application
    Filed: October 5, 2016
    Publication date: April 20, 2017
    Inventor: MING-CHIEH HSU
  • Publication number: 20160218131
    Abstract: A photo diode includes a pixel unit, a photo conversion layer, and a dielectric layer. The pixel unit includes a pair of pixels. The photo conversion layer is above the pixel unit and has a pair of portions, each of which corresponds to a respective one of the pixels. The dielectric layer is between the portions of the photo conversion layer. A method of manufacturing the photo diode is also disclosed.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Inventors: TZU-JUI WANG, KENG-YU CHOU, CHUN-HAO CHUANG, MING-CHIEH HSU, REN-JIE LIN, JEN-CHENG LIU, DUN-NIAN YAUNG
  • Patent number: 9356069
    Abstract: A method for forming a photo diode is provided. The method includes: forming a first pair of electrodes and a second pair of electrodes over a substrate by using a conductive layer; forming a dielectric layer over the substrate; patterning the dielectric layer over the substrate; forming a photo conversion layer over the substrate; and forming a color filter layer over the photo conversion layer, wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a first pixel from a second portion of the color filter layer corresponding to a second pixel, and a refractive index of the dielectric layer is lower than a refractive index of the color filter layer, wherein the first pair of electrodes corresponds to the first pixel and the second pair of electrodes corresponds to the second pixel.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tzu-Jui Wang, Keng-Yu Chou, Chun-Hao Chuang, Ming-Chieh Hsu, Ren-Jie Lin, Jen-Cheng Liu, Dun-Nian Yaung