Patents by Inventor Ming Chieh Huang

Ming Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365479
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 10821413
    Abstract: A microparticle forming device is used to form microparticles with uniform particle size and proper roundness, and includes a collection pipe, a fluid nozzle, a reactor and a filter. The collection pipe includes a fluid passage, an aqueous-phase fluid inlet, an oil-phase fluid inlet and a mixed fluid outlet, all of which communicate with the fluid passage. The oil-phase fluid inlet is located between the aqueous-phase fluid inlet and the mixed fluid outlet. The fluid nozzle has a plurality of oil-phase fluid drop outlets aligned with the oil-phase fluid inlet of the collection pipe. The reactor has a reaction chamber communicating with the mixed fluid outlet of the collection pipe, a mixing member accommodated in the reaction chamber, and a microparticle collection port communicating communicated with the reaction chamber. Two opposite ends of the filter respectively communicate with the reaction chamber of the reactor.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 3, 2020
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Cheng-Han Hung, Zong-Hsin Liu, Ming-Fang Tsai, Ying-Chieh Lin, Chiu-Feng Lin, Ying-Cheng Lu, Yao-Kun Huang
  • Publication number: 20200324197
    Abstract: A gaming device includes a self-stabilizing module including a first portion and a second portion, a controller assembly disposed at the second portion, a motion sensor, an operation processing module, and a display screen disposed at the first portion. The operation processing module generates a frame signal to the display screen according to a program. The controller assembly and the second portion rotate about at least one self-stabilizing axis relative to the first portion when the self-stabilizing module is activated. The motion sensor generates a control signal due to the relative rotation of the first and second portions. The operation processing module generates another frame signal corresponding to a movement posture of the controller assembly relative to the display screen according to the control signal and the program. The display screen is not located on a movement track of the controller assembly. A gaming controller is also provided.
    Type: Application
    Filed: February 20, 2020
    Publication date: October 15, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Hsuan Ho, Chuang-Yuan Cheng, Che-An Wu, Yu-Chiang Lo, Pao-Hsuan Shen, Chen-Cheng Wang, Chun-Chieh Chen, Ming-Hsien Wu, Chen-Yi Huang
  • Publication number: 20200324198
    Abstract: A gaming device including a self-stabilizing module with at least two self-stabilizing axes, a display assembled to the self-stabilizing module, a controller assembly assembled to the self-stabilizing module, a motion sensor, and a processing module is provided. A relative movement of the controller assembly and the display are generated via at least one self-stabilizing axis of the self-stabilizing module. The processing module generates a frame signal to transfer to the display according to a program. When the self-stabilizing module is activated and the relative movement is generated, the motion sensor generates a control signal to the processing module, and the processing module generate another frame signal, which correspondingly depicts a posture of the controller assembly relative to the display, to transfer to the display according to the control signal and the program. A gaming controller is also provided.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 15, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Hsuan Ho, Chuang-Yuan Cheng, Che-An Wu, Yu-Chiang Lo, Chen-Cheng Wang, Chun-Chieh Chen, Ming-Hsien Wu, Chen-Yi Huang
  • Patent number: 10796055
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10790235
    Abstract: An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10778203
    Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Chun Yang, Chih-Chang Lin, Ming-Chieh Huang
  • Publication number: 20200287528
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10770402
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20200274535
    Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10747938
    Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan Wu, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
  • Patent number: 10734299
    Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching Fu Chang
  • Patent number: 10719001
    Abstract: A smart lighting device includes an illumination module, an image projection module, a camera module, a sensing module and an identifying module. The illumination module is configured to provide illumination light beams. The image projection module is configured to project an image frame. The sensing module has a specific sensing area and is configured to sense an operation action of a user within the sensing area. The identifying module is electrically connected to the image projection module, the camera module and the sensing module. The camera module is configured to shoot a content to be identified to form an image to be identified. The identifying module is configured to identify the image to be identified. The image projection module is configured to display information acquired by the identifying module in the projected image frame. A control method for the smart lighting device is also provided.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 21, 2020
    Assignee: Compal Electronics, Inc.
    Inventors: Ming-Che Weng, Kun-Hsuan Chang, Yu-Hao Tseng, Hsin-Chieh Cheng, Jui-Tsen Huang
  • Patent number: 10686434
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10673437
    Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10666418
    Abstract: A smart phase switching method includes setting a first phase switching threshold, a convergence upper bound, and a convergence lower bound, sampling a received signal continuously for acquiring a phase offset accumulated value of the received signal during each period, updating the first phase switching threshold to generate a second phase switching upper bound threshold and a second phase switching lower bound threshold when a plurality of phase offset accumulated values of the received signal during a first predetermined time interval fall into a range from the convergence upper bound to the convergence lower bound, and sampling the received signal continuously for determining if a phase is switched to an opposite operating point according to a phase offset accumulated value of the received signal after the second phase switching upper bound threshold and the second phase switching lower bound threshold are generated.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: May 26, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yan-Guei Chen, Ming-Chieh Cheng, Liang-Wei Huang
  • Publication number: 20200135651
    Abstract: A package structure is provided. The package structure includes a redistribution layer and a first integrated circuit chip having a first chip edge and a second integrated circuit chip having a second chip edge over the redistribution layer. The package structure also includes first bumps electrically connected to the first integrated circuit chip through the redistribution layer. In addition, the first bumps overlap the first integrated circuit chip and are arranged along a first chip edge of the first integrated circuit chip. The package structure further includes second bumps electrically connected to the first integrated circuit chip through the redistribution layer without overlapping the first integrated circuit chip and the second integrated circuit chip. In addition, none of the second bumps is arranged between the first chip edge and the second chip edge.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Ming-Yen CHIU, Hsin-Chieh HUANG, Ching-Fu CHANG
  • Publication number: 20200107414
    Abstract: An LED (Light Emitting Diode) drive circuit includes a magnetic device, a power transistor, a current-sense resistor, and a controller. The magnetic device has a first terminal for receiving an input voltage derived from an input of the LED drive circuit, and a second terminal. The magnetic device generates an output current to drive at least one LED. The power transistor has a drain coupled to the second terminal of the magnetic device, a control terminal, and a source. The current-sense resistor has a first terminal coupled to the source of the power transistor for forming a current input signal, and a second terminal coupled to ground. The controller generates a switching signal coupled to control the power transistor to switch current through the magnetic device based on both a programmable signal derived from the input of the LED drive circuit, and the current input signal.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Ta-Yung YANG, Chuh-Ching LI, Ming-Chieh LEE, Kuo-Hsien HUANG
  • Patent number: 10605981
    Abstract: A light assembly, a backlight module and a liquid crystal display are described. The light assembly includes a carrier, a light guide plate, a light source, a constraining member and a securing unit. The light guide plate is disposed on the carrier and has an incident surface. The light source which emits light towards the light guide plate and is adjacent to the incident surface of the light guide plate. The constraining member is disposed above the carrier and has a constraining surface. The securing unit is used to combine the constraining member with the carrier while the light guide plate is restrained against movement by the constraining surface of the constraining member.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 31, 2020
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: Teng-Yi Huang, Ming-Cheng Lin, Yung-Chieh Chao
  • Patent number: 10600938
    Abstract: A light-emitting device includes: a light-emitting stack including a first active layer emitting a first light having a first peak wavelength; a diode emitting a second light having a second peak wavelength between 800 nm and 1900 nm; and a tunneling junction between the diode and the light-emitting stack, wherein the tunneling junction includes a first tunneling layer and a second tunneling layer on the first tunneling layer, the first tunneling layer has a band gap and a thickness of the first tunneling layer is greater than a thickness of the second tunneling layer.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 24, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Chiang Lu, Yi-Chieh Lin, Rong-Ren Lee, Yu-Ren Peng, Ming-Siang Huang, Ming-Ta Chin, Yi-Ching Lee