Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Abstract: Devices and methods for forming a chip package structure including a package substrate, a first adhesive layer attached to a top surface of the package substrate, and a beveled stiffener structure attached to the package substrate. The beveled stiffener structure may include a bottom portion including a tapered top surface, in which a bottom surface of the bottom portion is in contact with the first adhesive layer, a second adhesive layer attached to the tapered top surface, and a top portion including a tapered bottom surface, in which the tapered bottom surface is in contact with the second adhesive layer. The tapered top surface and the tapered bottom surface have a taper angle between 5 degrees and 60 degrees with respect to a top surface of the package substrate.

Abstract: A semiconductor structure includes a substrate, a first support layer, and multiple support pillars. The substrate includes a monitoring region. The monitoring region includes a first region and a second region. The first support layer is located in the first region and the second region, and is located above the substrate. The support pillars are located in the second region. The support pillars penetrate the first support layer and are not connected to each other. Each of the support pillars extends toward the substrate.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, bit lines disposed on the dielectric layer, spacers and a contact. The substrate has active areas arranged in parallel with each other. The bit lines are arranged in parallel with each other. Each bit line is partially overlapped with the corresponding active area. Each bit line has first portions and second portions arranged alternately in an extending direction thereof, and a width of the first portions is smaller than that of the second portions. The spacers are disposed on the sidewalls of each bit line. The contact is disposed between the adjacent bit lines and adjacent to the corresponding first portion of at least one of the adjacent bit lines, penetrates through the dielectric layer, and is in contact with the corresponding active area.

Abstract: A buried word line structure including a substrate, an isolation structure, and a buried word line is provided. The isolation structure is located in the substrate to define active regions separated from each other. The active regions extend in a first direction. The buried word line is located in the substrate. The buried word line extends through the isolation structure and the active regions in a second direction. The first direction intersects the second direction. The buried word line and the substrate are isolated from each other. The same buried word line includes a first portion and a second portion. The first portion is located in the active regions. The second portion is located in the isolation structure between two adjacent active regions in the first direction. A width of the first portion is greater than a width of the second portion.

Abstract: A buried word line structure including a substrate, an isolation structure, and a buried word line is provided. The isolation structure is located in the substrate to define active regions separated from each other. The active regions extend in a first direction. The buried word line is located in the substrate. The buried word line extends through the isolation structure and the active regions in a second direction. The first direction intersects the second direction. The buried word line and the substrate are isolated from each other. The same buried word line includes a first portion and a second portion. The first portion is located in the active regions. The second portion is located in the isolation structure between two adjacent active regions in the first direction. A width of the first portion is greater than a width of the second portion.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, bit lines disposed on the dielectric layer, spacers and a contact. The substrate has active areas arranged in parallel with each other. The bit lines are arranged in parallel with each other. Each bit line is partially overlapped with the corresponding active area. Each bit line has first portions and second portions arranged alternately in an extending direction thereof, and a width of the first portions is smaller than that of the second portions. The spacers are disposed on the sidewalls of each bit line. The contact is disposed between the adjacent bit lines and adjacent to the corresponding first portion of at least one of the adjacent bit lines, penetrates through the dielectric layer, and is in contact with the corresponding active area.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed around the gate structure, and an epitaxial layer is formed in the substrate adjacent to the spacer. Preferably, the step of forming the epitaxial layer further includes: forming a buffer layer in the substrate; forming a bulk layer on the buffer layer; forming a linear gradient cap on the bulk layer, and forming a silicon cap on the linear gradient cap. Preferably, the etching to deposition ratio of the linear gradient cap is greater than 50% and less than 100%.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; and forming an epitaxial layer on the substrate, in which an etching to deposition ratio of the epitaxial layer is greater than 50%.

Abstract: A power management system is disposed in a computer. The power management system includes a current detecting module and a chipset. The current detecting module is disposed between the power receiving end of an external device and the power cord of the power source of the computer for detecting the current sink by the external device and accordingly outputting a current detecting signal. The chipset adjusts the operating voltage or operating frequency of the external device according to the current detecting signal.

Abstract: A power management system is disposed in a computer. The power management system includes a current detecting module and a chipset. The current detecting module is disposed between the power receiving end of an external device and the power cord of the power source of the computer for detecting the current sink by the external device and accordingly outputting a current detecting signal. The chipset adjusts the operating voltage or operating frequency of the external device according to the current detecting signal.

Abstract: A universal slot disposed on a base plate includes a first slot and a second slot. The first slot has a first electrical characteristic, and the second slot has a second electrical characteristic. The second slot covers the first slot in appearance.

Abstract: A universal slot disposed on a base plate includes a first slot and a second slot. The first slot has a first electrical characteristic, and the second slot has a second electrical characteristic. The second slot covers the first slot in appearance.

Abstract: A slot device has a slot, a determining circuit, and a warning device. The slot is used to install an expansion card. The determining circuit is coupled to the slot and is used to determine whether the expansion card is completely installed to the slot. The warning device is coupled to the determining circuit, and when the determining circuit determines that the expansion card is not completely installed to the slot, the determining circuit controls the warning device to send out a warning signal.