Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.

Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.

Abstract: An apparatus includes a six-axis correction stage, an auto-collimation measurement device, a light splitter, a telecentric image measurement device, and a controller. The six-axis correction stage carries a device under test; the auto-collimation measurement device is arranged above the six-axis correction stage along a measurement optical axis; the light splitter is arranged on the measurement optical axis and is interposed between the six-axis correction stage and the auto-collimation measurement device. A method controls the six-axis correction stage to correct rotation errors in at least two degrees of freedom of the device under test according to a measurement result of the auto-collimation measurement device, and controls the six-axis correction stage to correct translation and yaw errors in at least three degrees of freedom of the device under test according to a measurement result of the telecentric image measurement device by means of the controller.

Abstract: A frequency shift detector includes a digital control unit, a digital/analog converter, a reagent concentration detecting circuit and a frequency difference generator, wherein the digital control unit includes a control circuit and a direct digital frequency synthesizer electrically connected with the control circuit, and the control circuit comprises a reset terminal and a pulse input terminal. The digital control unit proceeds with accurate concentration detection for various samples borne on the reagent concentration detecting circuit.

Abstract: A magnetic interface circuit (100) includes a pair of channels (101, 102) and an absorb network (3). Each channel includes a 3-wire common mode choke (2) having a middle tap (21), and an isolation transformer (1) connected with the 3-wire common mode choke. The isolation transformer has a primary winding (11) and a secondary winding (12) each having a pair of first output taps (111, 121) and a first center tap (13, 14). The absorb network includes a bridge rectifying circuit (4) adapted for converting an electrical current. Each bridge rectifying circuit has a pair of input taps (45, 46) each connected with corresponding center taps of the isolation transformers, and a pair of output taps (47, 48).

Abstract: A magnetic interface circuit (100) includes a pair of channels (101, 102) and an absorb network (3). Each channel includes a 3-wire common mode choke (2) having a middle tap (21), and an isolation transformer (1) connected with the 3-wire common mode choke. The isolation transformer has a primary winding (11) and a secondary winding (12) each having a pair of first output taps (111, 121) and a first center tap (13, 14). The absorb network includes a bridge rectifying circuit (4) adapted for converting an electrical current. Each bridge rectifying circuit has a pair of input taps (45, 46) each connected with corresponding center taps of the isolation transformers, and a pair of output taps (47, 48).

Abstract: Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

Abstract: A modular connector for electrically connecting a modular plug to a mother board includes an insulative housing having a vertical front mating face and an electrical module mounted in the housing. The electrical module includes a front PCB parallel the mating face, two mutual parallel second electric circuit boards perpendicularly connecting to the front PCB, and a number of magnetic coils directly mounted on the rear PCBs.

Abstract: A modular connector for electrically connecting a modular plug to a mother board includes an insulative housing having a vertical front mating face and an electrical module mounted in the housing. The electrical module includes a front PCB parallel the mating face, two mutual parallel second electric circuit boards perpendicularly connecting to the front PCB, and a number of magnetic coils directly mounted on the rear PCBs.

Abstract: Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

Abstract: Zincselenide (ZnSe) thin films were grown on quartz glass and GaAs(100) substrates by continuous wave (CW) CO2 laser with ion beam assisted deposition. The ZnSe thin films are applied for multilayer anti-reflection coatings and blue light emitting devices. There are advantages to this technique over the Ion-Beam coating, MBE, MOCVD and PLD methods for fabricating layered semiconductors. It is cheaper and safer than Ion-Beam coating, MBE, MOCVD and others. It is cheaper and safer to heat the target locally by using a continuous wave laser so that contaminations and heat radiation are reduced. It is also cheaper and safer to avoid the splash of PLD.

Abstract: A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than the number of nodes in the problem space. The system partitions the memory of each physical processor cell into several equal sections, each section being associated with one node of the problem space. The instruction generator then produces a sequence of processor cell instructions for each node of the given problem space, with appropriate address modifications for each sequence of instructions provided by an address relocation circuit.

Abstract: A multi-dimensional processor cell and processor array with massively parallel input/output includes a processor array having a plurality of processor cells interconnected to form an N-dimensional array. The system includes a first group of processor cells having 2N dimensionally adjacent processor cells. At least one input/output device is connected to a surplus data signal port of a second group of processor cells each having fewer than 2N dimensionally adjacent processor cells, for providing massively parallel input/output between the multi-dimensional processor array and the input/output device. The processor system also includes a front end processor for providing processor array instructions in response to application programs running on the front end processor. A processor cell controller, responsive to the processor array commands, broadcasts a sequence of processor cell instructions to all of the processor cells of the multi-dimensional processor array.

Abstract: A reconfigurable multi-dimensional processor array for processing multi-dimensionally structured data includes a plurality of processor cells arranged in N dimensions and having a plurality of N-1 dimensional processor subarrays. Each of the processor cells has 2N data signal ports operative for forming data signal paths for transmitting and receiving data to and from 2N adjacent processor cells or data communication devices. Each of the N-1 dimensional processor subarrays includes a selected group of processor cells coupled to fewer than 2N other processor cells or data communications devices. Each of the selected group of processor cells includes at least one uncoupled data signal port.