Patents by Inventor Ming-Chih WU

Ming-Chih WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230090794
    Abstract: An electronic device for controlling an LRA (Linear Resonant Actuator) includes a signal generator, a driver, a delay unit, a sensor, and a DSP (Digital Signal Processor). The signal generator generates a digital signal. The driver drives the LRA according to the digital signal. The delay unit delays the digital signal for a predetermined time, so as to generate an estimated voltage signal. The sensor detects the current flowing through the LRA, so as to generate a sensing current signal. The DSP controls the resonant frequency or the gain value of the signal generator according to the estimated voltage signal and the sensing current signal.
    Type: Application
    Filed: October 28, 2021
    Publication date: March 23, 2023
    Inventors: Tsung-Han YANG, Yen-Chih WANG, Ming-Jun HSIAO, Tsung-Nan WU
  • Publication number: 20230056353
    Abstract: A micro scanning mirror, including a fixed substrate, a lens, and multiple cantilevers, are provided. Each cantilever includes a piezoelectric material structure, multiple first drive electrodes, and multiple second drive electrodes. The piezoelectric material structure includes a connecting part, a folding part, and a fixed part. The connecting part connects the lens along a direction parallel to a central axis of the lens. The folding part has a bending region and multiple drive electrode regions. The fixed part is connected to the fixed substrate, and the folding part is connected to the connecting part and the fixed part. The first drive electrodes and the second drive electrodes are respectively located in the corresponding drive electrode regions in the folding part. The micro scanning mirror of the disclosure can drive a large-sized micro mirror to rotate at an appropriate rotation angle.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 23, 2023
    Applicant: Coretronic MEMS Corporation
    Inventors: Shih-Chi Liu, Wei-Leun Fang, Kai-Chih Liang, Kai-Chieh Chang, Ming-Ching Wu
  • Publication number: 20230008519
    Abstract: An automatic vehicle positioning management system includes an on-vehicle apparatus and a portable device. The on-vehicle apparatus, installed on a vehicle, acquires a first location of the vehicle through wireless positioning. The first location is sent to the portable device which acquires a second location of the vehicle through GPS. When multiple vehicles form a fleet, each vehicle respectively sends its first and second locations to a server through its portable device. The second location of each vehicle is corrected by operations of point error analysis, image overlay and point error correction, so that the fleet can be managed more precisely.
    Type: Application
    Filed: July 7, 2021
    Publication date: January 12, 2023
    Inventors: HSIU-LING HUANG, WEI-CHIH WU, MING-CHIEH LIN
  • Patent number: 11527439
    Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20220359377
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Publication number: 20220359292
    Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20220359284
    Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh, An-Jhih Su
  • Patent number: 11476699
    Abstract: A power backup circuit provides a plurality of input power sources to back up a load. The power backup circuit includes a first switch, a second switch, and a control unit. The input power sources at least includes a first input power source and a second input power source. If the input power source of the load needs to be changed from the first input power source to the second input power source, the control unit controls the first switch to be coupled to the second input power source and controls the second switch to be coupled to the second input power source after the control unit effects a supply current flowing through a first power supply path and a second power supply path both coupled to the first input power source and the load to be reduced below a current threshold.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 18, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Te-Chih Peng, Ming-Hsiang Lo, Chih-Hong Wu, Yu-Ren Weng
  • Patent number: 11469138
    Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh, An-Jhih Su
  • Patent number: 11459354
    Abstract: The present invention provides improved processes for purifying liraglutide. Liraglutide is purified via two sequential RP-HPLC purifications followed by a salt-exchange step, where a pH is kept constant in the first and second purification steps. In particular, the processes utilize a halogenated solvent in a sample preparation step, which provides better solubility and an environment suitable for decarboxylation for crude liraglutide prior to a RP-HPLC purification.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 4, 2022
    Assignee: ScinoPharm Taiwan, Ltd.
    Inventors: Ming-Chih Wu, Hsin-Che Huang, Tsung-Yu Hsiao
  • Publication number: 20220302110
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
  • Patent number: 11444020
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Patent number: 11404413
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
  • Publication number: 20210206800
    Abstract: The present invention provides improved processes for purifying semaglutide or liraglutide. Semaglutide or liraglutide is purified via two sequential RP-HPLC purifications followed by a salt-exchange step, where a pH is kept constant in the first and second purification steps. In particular, the processes utilize a halogenated solvent in a sample preparation step, which provides better solubility and an environment suitable for decarboxylation for crude semaglutide or liraglutide prior to a RP-HPLC purification.
    Type: Application
    Filed: February 8, 2021
    Publication date: July 8, 2021
    Inventors: Ming-Chih WU, Tsung-Yu Hsiao
  • Publication number: 20200308218
    Abstract: The present invention provides improved processes for purifying liraglutide. Liraglutide is purified via two sequential RP-HPLC purifications followed by a salt-exchange step, where a pH is kept constant in the first and second purification steps. In particular, the processes utilize a halogenated solvent in a sample preparation step, which provides better solubility and an environment suitable for decarboxylation for crude liraglutide prior to a RP-HPLC purification.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Inventors: Ming-Chih WU, Hsin-Che HUANG, Tsung-Yu HSIAO
  • Patent number: 10435395
    Abstract: Crystalline form S1 of lifitegrast characterized by a powder X-ray diffraction pattern with peaks at about 10.7±0.2, 16.2±0.2, 19.9±0.2, 22.1±0.2, 24.7±0.2, and 25.9±0.2 degrees two-theta, crystalline form S2 of lifitegrast characterized by a powder X-ray diffraction pattern with peaks at about 16.4±0.2, 24.9±0.2, and 26.2±0.2 degrees two-theta, and processes of making thereof are provided.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 8, 2019
    Assignee: SCINOPHARM TAIWAN, LTD.
    Inventors: Wen-Wei Lin, Tsung-Cheng Hu, YuanChang Huang, Ming-Chih Wu
  • Publication number: 20190300512
    Abstract: Crystalline form S1 of lifitegrast characterized by a powder X-ray diffraction pattern with peaks at about 10.7±0.2, 16.2±0.2, 19.9±0.2, 22.1±0.2, 24.7±0.2, and 25.9±0.2 degrees two-theta, crystalline form S2 of lifitegrast characterized by a powder X-ray diffraction pattern with peaks at about 16.4±0.2, 24.9±0.2, and 26.2±0.2 degrees two-theta, and processes of making thereof are provided.
    Type: Application
    Filed: March 8, 2019
    Publication date: October 3, 2019
    Inventors: Wen-Wei Lin, Tsung-Cheng Hu, YuanChang Huang, Ming-Chih Wu
  • Patent number: 10428052
    Abstract: The present disclosure provides efficient, economical, and improved processes for synthesizing lifitegrast and intermediates thereof. The currently discloses processes provide a direct synthetic route, avoiding protection or deprotection steps. The currently disclosed process also provides processes for synthesizing lifitegrast using a reduced number of synthetic steps.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 1, 2019
    Assignee: ScinoPharm Taiwan, Ltd.
    Inventors: Ming-Chih Wu, Tsung-Yu Hsiao
  • Publication number: 20190002445
    Abstract: The present disclosure provides efficient, economical, and improved processes for synthesizing lifitegrast and intermediates thereof. The currently discloses processes provide a direct synthetic route, avoiding protection or deprotection steps. The currently disclosed process also provides processes for synthesizing lifitegrast using a reduced number of synthetic steps.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 3, 2019
    Inventors: Ming-Chih WU, Tsung-Yu HSIAO
  • Patent number: 9609378
    Abstract: An IP camera, a communication method and a communication system are provided. The IP camera includes an image capturing unit, a video processing unit and a connection processing unit. The image capturing unit captures a plurality of consecutive images. The video processing unit is coupled to the image capturing unit, and generates a first video stream and a second video stream according to the images. The connection processing unit is coupled to the video processing unit, processes the first video stream into a first packet stream, and processes the second video stream into a second packet stream. The connection processing unit transmits the first packet stream to a local area wireless network unit through a first wireless link, and the connection processing unit transmits the second packet stream to an external electronic device through a second wireless link.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 28, 2017
    Assignee: SONIX Technology Co., Ltd.
    Inventors: Chung-Chih Ko, Ming-Chih Wu, Kun-Ming Huang