Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a reinforcing structure over the circuit substrate. The reinforcing structure partially surrounds a corner of the die package. The package structure further includes an underfill structure surrounding the bonding structure. The underfill structure is in direct contact with the reinforcing structure.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate, a semiconductor device, an underfill element, and a groove. The semiconductor device is bonded to the surface of the package substrate through multiple electrical connectors. The underfill element is formed between the semiconductor device and the surface of the package substrate to surround and protect the electrical connectors. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The groove is formed in the fillet portion and spaced apart from the periphery of the semiconductor device.

Abstract: A semiconductor package structure includes a first bottom electrical connector, an interposer over the first bottom electrical connector, and a first top electrical connector over the first top via structures. The interposer includes first bottom via structures in contact with the first bottom electrical connector. The interposer also includes a first trace of a first redistribution layer structure over the first bottom via structures. The interposer also includes first via structures over the first redistribution layer. The interposer also includes a first trace of a second redistribution layer structure over the first via structures. The interposer also includes second via structures over the second redistribution layer structure. The first bottom via structures, the first via structures, and the second via structures are separated from each other in a top view.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A redistribution structure is formed. An encapsulated semiconductor device is provided on a first side of the redistribution structure, wherein the encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material. A substrate is bonded to a second side of the redistribution structure opposite to the first side. The redistribution structure includes a plurality of vias connected to one another through a plurality of conductive lines and a redistribution line connected to the plurality of vias, and, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines.

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

Abstract: A package structure is provided. The package structure includes a redistribution structure over a substrate, a semiconductor die over the redistribution structure and electrically coupled to the substrate, and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die. The underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate.

Abstract: Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Abstract: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.

Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: Devices and methods for forming a chip package structure including a package substrate, a first adhesive layer attached to a top surface of the package substrate, and a beveled stiffener structure attached to the package substrate. The beveled stiffener structure may include a bottom portion including a tapered top surface, in which a bottom surface of the bottom portion is in contact with the first adhesive layer, a second adhesive layer attached to the tapered top surface, and a top portion including a tapered bottom surface, in which the tapered bottom surface is in contact with the second adhesive layer. The tapered top surface and the tapered bottom surface have a taper angle between 5 degrees and 60 degrees with respect to a top surface of the package substrate.

Abstract: A method includes forming a first redistribution structure over a carrier, where forming the first redistribution structure includes forming a plurality of first organic polymer layers over the carrier, and forming a plurality of first conductive lines in the plurality of first organic polymer layers, attaching a first package structure to the first redistribution structure, the first package structure including a first semiconductor die, a molding material that surrounds an entirety of a perimeter of the first semiconductor die, and a second redistribution structure on bottom surfaces of the first semiconductor die and the molding material, dispensing a first underfill into a first gap between the plurality of first conductive lines and the first package structure, bonding a substrate to the first redistribution structure using first conductive connectors, and dispensing a second underfill into a second gap between the substrate and the first redistribution structure.

Abstract: A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Abstract: A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.

Abstract: A semiconductor package includes a package substrate; a semiconductor die vertically stacked on the package substrate; a redistribution layer (RDL) including a dielectric material and metal features that electrically connect the semiconductor die to the package substrate, the RDL having a first Young's modulus; a first underfill layer disposed between the RDL and the semiconductor die; and stress buffers embedded in the RDL below corners of the semiconductor die, each stress buffer having a second Youngs modulus that is at least 30% less than the first Youngs modulus.

Abstract: A semiconductor package includes a die, a redistribution structure and a plurality of conductive terminals. The redistribution structure is disposed below and electrically connected to the die. The redistribution structure includes a plurality of conductive patterns, and at least one of the plurality of conductive patterns has a cross-section substantially parallel to the surface of the die. The cross-section has a long-axis and a short-axis, and the long-axis intersects with a center axis of the die. The conductive terminals are disposed below and electrically connected to the redistribution structure.

Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

Abstract: A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.