Patents by Inventor Ming-Ching Chang

Ming-Ching Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220238387
    Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220238696
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20220223587
    Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Publication number: 20220216322
    Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11315272
    Abstract: The present approach relates to an automatic and efficient motion plan for a drone to collect and save a qualified dataset that may be used to improve reconstruction of 3D models using the acquired data. The present architecture provides an automatic image processing context, eliminating low quality images and providing improved image data for point cloud generation and texture mapping.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: April 26, 2022
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Ming-Ching Chang, Junli Ping, Eric Michael Gros, Arpit Jain, Peter Henry Tu
  • Patent number: 11309403
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11302581
    Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11289585
    Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11205647
    Abstract: A semiconductor device and method are provided whereby a series of spacers are formed in a first region and a second region of a substrate. The series of spacers in the first region are patterned while the series of spacers in the second region are protected in order to separate the properties of the spacers in the first region from the properties of the spacers in the second region.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chi-Sheng Lai, Chih-Han Lin, Wei-Chung Sun, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20210367058
    Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.
    Type: Application
    Filed: September 11, 2020
    Publication date: November 25, 2021
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20210359109
    Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
    Type: Application
    Filed: November 23, 2020
    Publication date: November 18, 2021
    Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20210351281
    Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11152249
    Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jih-Jse Lin, Ryan Chia-Jen Chen, Fang-Cheng Chen, Ming-Ching Chang
  • Patent number: 11145051
    Abstract: The present approach relates to the use of a point cloud of an object to initialize or seed a space carving technique used to generate a 3D model of the object. In one implementation, feature matching is performed on 2D images, with matched features constituting the points of a point cloud model. The point cloud generated in this manner, is one input of a foreground/background segmentation algorithm, which generates a set of segmented 2D images used by a space carving routine to generate a 3D model of the object.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 12, 2021
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Eric Michael Gros, Junli Ping, Arpit Jain, Ming-Ching Chang, Peter Henry Tu
  • Publication number: 20210313450
    Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.
    Type: Application
    Filed: June 11, 2021
    Publication date: October 7, 2021
    Inventors: Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 11133307
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Publication number: 20210296181
    Abstract: The first and second fins extend upwardly from a semiconductor substrate. The shallow trench isolation structure laterally surrounds lower portions of the first and second fins. The first gate structure extends across an upper portion of the first fin. The second gate structure extends across an upper portion of the second fin. The first source/drain epitaxial structures are on the first fin and on opposite sides of the first gate structure. The second source/drain epitaxial structures are on the second fin and on opposite sides of the second gate structure. The separation plug interposes the first and second gate structures and extends along a lengthwise direction of the first fin. The isolation material cups an underside of a portion of the separation plug between one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang HUNG, Shu-Yuan KU, I-Wei YANG, Yi-Hsuan HSIAO, Ming-Ching CHANG, Ryan Chia-Jen CHEN
  • Publication number: 20210296484
    Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Chang-Yun Chang, Ming-Ching Chang, Shu-Yuan Ku
  • Patent number: 11127741
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Publication number: 20210280695
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 9, 2021
    Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang