Patents by Inventor Ming-Ching Chang

Ming-Ching Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261170
    Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Publication number: 20250089328
    Abstract: Semiconductor devices and methods for forming the semiconductor devices using a cap layer are provided. The semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a gate spacer that extends along a sidewall of the upper portion of the gate structure. In some examples, a gap dimension measured between the gate spacer and an adjacent one of the plurality of semiconductor layers is sufficiently small such that the gate structure does not contact the source/drain structures. In some examples, the gate spacer and an adjacent one of the one or more semiconductor layers of the fin structure are separated by a cap layer.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chiung-Yu Cho, Chih-Han Lin, Ming-Ching Chang
  • Publication number: 20250086497
    Abstract: A machine learning training device is disclosed. The machine learning training device includes a virtual hard anchor generation circuit, a classification circuit and a training circuit. The virtual hard anchor generation circuit is configured to generate several virtual hard anchors according to several easy samples classified into several types. The virtual hard anchors respectively correspond to one of the several types. The classification circuit is configured to classify several hard samples into several types according to virtual hard anchors. Parts of the hard samples classified into several types are several clean hard samples. Another parts of the hard samples that are not classified into several types are several noisy hard samples. The training circuit is configured to perform machine learning training according to several easy samples and several clean hard samples.
    Type: Application
    Filed: January 21, 2024
    Publication date: March 13, 2025
    Inventors: Po Hsuan HUANG, Chia-Ching LIN, Chih-Fan HSU, Ming-Ching CHANG, Wei-Chao CHEN
  • Publication number: 20250086437
    Abstract: An operating method of a fully homomorphic encrypted neural network model is provided, wherein the fully homomorphic encrypted neural network model includes a plurality of layers, and the method performed by a processor includes: for one of the plurality of layers, encrypting a plaintext input with a first encryption algorithm to generate a ciphertext vector, performing a convolution operation according to the ciphertext vector to generate a result vector, transforming the result vector into a plurality of result ciphertexts adopting a second encryption algorithm, inputting the plurality of result ciphertexts into an activation function to generate a plurality of encrypted activation values, and repacking the plurality of encrypted activation values to generate an output vector adopting the first encryption algorithm.
    Type: Application
    Filed: December 19, 2023
    Publication date: March 13, 2025
    Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Tzu-Li LIU, Yu-Te KU, Ming-Chien HO, Chih-Fan HSU, Wei-Chao CHEN, Feng-Hao LIU, Ming-Ching CHANG, Shih-Hao HUNG
  • Publication number: 20250084274
    Abstract: A curable composition includes an epoxy monomer component and an aniline-based hardener. The epoxy monomer component is a first component formed from a first epoxy monomer represented by Formula (I), or a second component including the first epoxy monomer represented by Formula (I) and a second epoxy monomer different from the first epoxy monomer represented by Formula (I), wherein each of the substituents in Formula (I) is given the definitions as set forth in the Specification and Claims. Based on 100 wt % of the epoxy monomer component, an amount of the first epoxy monomer represented by Formula (I) is not smaller than 25 wt % and less than 100 wt % and an amount of the second epoxy monomer is greater than 0% and not greater than 75 wt %. A cured product formed from the curable composition, and a method for encapsulating a semiconductor device using the curable composition are also provided.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 13, 2025
    Inventors: Yun-Ching WU, Yu-Lin HUANG, Ming-Tsung TSAI, Pei-Nung CHEN, Shu-Wei CHANG, Ming-Tsung HSU
  • Publication number: 20250081587
    Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.
    Type: Application
    Filed: November 14, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Publication number: 20250080320
    Abstract: An inference method for encrypted deep neural network model is executed by a computing device and includes: encoding a message according to a quantization parameter to generate a plaintext, encrypting the plaintext according to a private key to generate a ciphertext, sending the ciphertext to a deep neural network model to generate a ciphertext result, decrypting the ciphertext result according to the private key to generate a plaintext result, and decoding the plaintext result according to the quantization parameter to generate an inference result.
    Type: Application
    Filed: January 10, 2024
    Publication date: March 6, 2025
    Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Yu-Te KU, Chih-Fan HSU, Wei-Chao CHEN, Feng-Hao LIU, Ming-Ching CHANG, Shih-Hao HUNG
  • Publication number: 20250081532
    Abstract: A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Ming-Ching Chang
  • Publication number: 20250081527
    Abstract: Semiconductor devices and methods for forming the semiconductor devices using diffusion cap layers are provided. The semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a plurality of diffusion cap layers disposed between and separating the plurality of semiconductor layers and the gate structure. In some embodiments, the plurality of diffusion cap layers function as diffusion barriers for the plurality of semiconductor layers.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chiung-Yu Cho, Ming-Ching Chang
  • Patent number: 12243748
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20250072099
    Abstract: Provided are devices and methods for forming devices. A method includes forming structures over a substrate; forming a layer between the structures; performing a first etch process to recess the layer to a surface having a serrated profile; optionally forming a film or films over the surface, wherein the film or films retain the serrated profile; depositing a material over the substrate; selectively masking the material to define a masked portion of the material and an unmasked portion of the material; and performing a second etch process to etch a portion of the material and form the material with a sidewall, wherein the second etch process uncovers the serrated profile, and wherein during the second etch process ions are reflected from the serrated profile.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chiung-Yu Cho, Ming-Ching Chang
  • Publication number: 20250071473
    Abstract: A speaker module includes a casing, a speaker unit and a vibration absorber. The speaker unit has a sound cavity. The speaker unit is disposed on the casing, and the speaker unit includes a first diaphragm. The vibration absorber is disposed in the casing, and the vibration absorber has a second diaphragm. When the first diaphragm vibrates, the airflow generated by the first diaphragm drives the second diaphragm to vibrate, and the vibration direction of the second diaphragm is opposite to the vibration direction of the first diaphragm, so as to absorb the vibration generated by the first diaphragm to the casing.
    Type: Application
    Filed: February 1, 2024
    Publication date: February 27, 2025
    Inventors: Jia-Ren CHANG, Ming-Chun FANG, Ruey-Ching SHYU, Chien-Chung CHEN
  • Patent number: 12230545
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20250040214
    Abstract: A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chiung-Yu Cho, Po-Yuan Tseng, Min-Chiao Lin, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang
  • Publication number: 20250022914
    Abstract: A method of forming a nanosheet FET is provided. A plurality of first and second semiconductor layers are alternately formed on a substrate. The first and second semiconductor layers are patterned into a plurality of stacks of semiconductor layers separate from each other by a space along a direction. Each stack of semiconductor layers has a cross-sectional view along the direction gradually widening towards the substrate. An epitaxial feature is formed in each of the spaces. The patterned second semiconductor layers are then removed from each of the stacks of semiconductor layers.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chiung-Yu CHO, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG
  • Patent number: 12198984
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.
    Type: Grant
    Filed: January 30, 2024
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
  • Patent number: 12199151
    Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.
    Type: Grant
    Filed: January 30, 2024
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 12176409
    Abstract: A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Ming-Ching Chang
  • Patent number: 12176412
    Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Publication number: 20240387680
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen