Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

Abstract: Provided is a method for forming semiconductor devices. This method includes forming a stack over a substrate. The stack includes multiple semiconductor portions spaced apart from one another by gaps. Next, the gaps are filled with a dielectric oxide material. End portions of the deposited dielectric oxide material are then laterally etched by an etch gas composition to form lateral openings. The etch gas composition includes a halogen-containing compound, ammonia and an amine. After forming inner spacers in the lateral openings between the adjacent semiconductor portions of the multiple semiconductor portions, the remaining portions of the deposited dielectric oxide material in the gaps are moved. A gate stack is then formed in the gaps to surround a channel region of the stack.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

Abstract: The present disclosure provides a method including: generating a first private key and a public key according to a parameter set of full homomorphic encryption; encrypting test data and label by the public key to generate test data ciphertext and label ciphertext; generating a smart contract executed by a blockchain system, and transferring control of an amount of cryptocurrency from a first cryptocurrency account to the blockchain; receiving a result of a verification to a model ciphertext; when the result indicates that the model ciphertext does not pass the verification, retrieving the control of the amount of cryptocurrency; and when the result indicates that the model ciphertext passes the verification, receiving the model ciphertext and a second private key from the blockchain system, and decrypting, according to the first and second private keys, the model ciphertext to generate a model to infer the test data.

Abstract: A method and system for reducing hallucinations generated by a Large Vision-Language Model (LVLM) are provided. The method includes a plurality of steps performed by a computing device, and these steps include: obtaining a test image, inputting the test image and a prompt into the LVLM to generate a test embedding, where the prompt instructs the LVLM to describe the test image, identifying a candidate embedding closest to the test embedding among a plurality of reference embeddings, replacing data of the test embedding in a salient dimension with data of the candidate embedding in the salient dimension, and generating a test result by the LVLM according to the test embedding with replaced data.

Abstract: An inference method for encrypted deep neural network model is executed by a computing device and includes: encoding a message according to a quantization parameter to generate a plaintext, encrypting the plaintext according to a private key to generate a ciphertext, sending the ciphertext to a deep neural network model to generate a ciphertext result, decrypting the ciphertext result according to the private key to generate a plaintext result, and decoding the plaintext result according to the quantization parameter to generate an inference result.

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first channel and a second gate segment is disposed over the second channel. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

Abstract: A training method for continual learning model and a non-transitory computer-readable medium are proposed. The method includes: training the encoder and self-attention layer in the essence generation procedure according to the raw data of a task when the current training process is the first task in continual learning; otherwise, freezing the parameters of the encoder and self-attention layer, performing the essence generation procedure to convert the raw data into a data essence, and adding the data essence into the essence memory. The training process is repeated until the continual learning model converges. The training process includes: obtaining a training batch from the raw data, updating the replay memory according to the training batch, training the continual learning model according to the replay memory and the essence memory, and updating the data essence in the essence memory when the current training process is the first task.

Abstract: The accelerated bootstrapping fully homomorphic encryption calculator includes a memory, a controller, a task scheduler, a plurality of processing units, and a bus. The memory stores ciphertext structured as learning with errors over rings. The controller manages storing the ciphertext and generates instructions for bootstrapping. The task scheduler organizes tasks based on the controller's instructions, and the processing units decompose the ciphertext and perform computations to generate intermediate or final results. The bus connects all components and handles the transmission of ciphertext, instructions, and results.

Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.

Abstract: Embodiments of the present disclosure provide methods for forming semiconductor device structures. The method includes forming a fin structure from a substrate, and the fin structure includes alternating first and second semiconductor layers. The method further includes removing edge portions of each of the second semiconductor layers, depositing an insulating material around the fin structure, performing a thermal process to expand the second semiconductor layers laterally, forming a sacrificial gate structure over a portion of the fin structure, recessing an exposed portion of the fin structure, and forming a source/drain region over the recessed portion of the fin structure.

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

Abstract: A semiconductor device and method of forming thereof includes a first fin and a second fin each extending from a substrate. A first gate segment is disposed over the first channel and a second gate segment is disposed over the second channel. An interlayer dielectric (ILD) layer is adjacent the first gate segment and the second gate segment. A cut region (e.g., opening or gap between first gate structure and the second gate structure) extends between the first and second gate segments. The cut region has a first portion has a first width and a second portion has a second width, the second width is greater than the first width. The second portion interposes the first and second gate segments and the first portion is defined within the ILD layer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a fin structure extending along a first lateral direction; forming a dummy gate structure that is over a portion of the fin structure and extends along a second direction perpendicular to the first lateral direction; growing source/drain structures that are respectively coupled to ends of the portion of the fin structure; removing the dummy gate structure to form a gate trench; lining inner sidewalls of the gate trench with a gate spacer; and forming an active gate structure in the gate trench.

Abstract: Provided are devices with replacement structures. A device includes a semiconductor structure and an isolation adjacent to the semiconductor structure, wherein the isolation includes a first region having an upper surface at a first height, wherein the isolation includes a second region having an upper surface at a second height, wherein the first height is equal to the second height plus 3 to 20 nanometers (nm); a conductive gate located over the semiconductor structure and over the first region of the isolation at the first height; and a source/drain region located over the second region of the isolation at the second height.

Abstract: Provided are devices with replacement structures and methods for fabricating such structures. A method includes forming a layer over a semiconductor material having a top surface in a horizontal plane; forming a dummy structure over the layer, wherein the dummy structure has sidewall, wherein the dummy structure lies directly over a first region of the layer and over a first region of the semiconductor material under the first region of the layer, and wherein the dummy structure does not lie directly over a second region of the layer or over a second region of the semiconductor material under the second region of the layer, and removing the second region of the layer and forming a side edge of the first region of the layer, wherein the side edge forms an angle of from 90 to 100 degrees with the horizontal plane.

Abstract: A method includes forming a dummy gate electrode on a semiconductor region, forming a first gate spacer on a sidewall of the dummy gate electrode, and removing an upper portion of the first gate spacer to form a recess, wherein a lower portion of the first gate spacer remains, filling the recess with a second gate spacer, removing the dummy gate electrode to form a trench, and forming a replacement gate electrode in the trench.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes first and second source/drain regions disposed over a substrate and an isolation region disposed between the first and second source/drain regions. The isolation region includes a first top surface having a slanted portion and a flat portion, and a portion of the isolation region located between the slanted portion of the first top surface and a plane defined by the flat portion of the first top surface has a width and a height. The width is greater than the height. The structure further includes a plurality of semiconductor layers disposed adjacent the first and second source/drain regions, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a spacer disposed between the gate electrode layer and the first source/drain region.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.