Abstract: A system for controlling excess bias of a single photon avalanche photo diode (SPAD) is provided. The system includes a power supply, a SPAD, a control circuit and a load. The power supply generates a supply voltage. The SPAD has a first terminal receiving the supply voltage and a second terminal generating an output voltage signal. The control circuit is connected to the second terminal of the SPAD. The load has a first terminal connected to the second terminal of the SPAD, and a second terminal connected to the control circuit for receiving a reset level. The control circuit is capable of monitoring a swing of the output voltage level and generating the reset level in response to the excess bias level and the swing of the output voltage level.

Abstract: A system for controlling excess bias of a single photon avalanche photo diode (SPAD) is provided. The system includes a power supply, a SPAD, a control circuit and a load. The power supply generates a supply voltage. The SPAD has a first terminal receiving the supply voltage and a second terminal generating an output voltage signal. The control circuit is connected to the second terminal of the SPAD. The load has a first terminal connected to the second terminal of the SPAD, and a second terminal connected to the control circuit for receiving a reset level. The control circuit is capable of monitoring a swing of the output voltage level and generating the reset level in response to the excess bias level and the swing of the output voltage level.

Abstract: The noise figure of a low noise amplifier (LNA) is reduced without sacrificing performance such as gain, IIP3, and wideband impedance matching. Embodiments include configuring a control module of the LNA to sum and scale an output from a current-sensing branch of the LNA and an output from a voltage sensing branch of the LNA into one or more summed and scaled outputs. The control module also feeds the one or more summed and scaled outputs back to at least one of the outputs of the branches of the LNA.

Abstract: The noise figure of a low noise amplifier (LNA) is reduced without sacrificing performance such as gain, IIP3, and wideband impedance matching. Embodiments include configuring a control module of the LNA to sum and scale an output from a current-sensing branch of the LNA and an output from a voltage sensing branch of the LNA into one or more summed and scaled outputs. The control module also feeds the one or more summed and scaled outputs back to at least one of the outputs of the branches of the LNA.

Abstract: A DC offset calibration apparatus including a signal processing unit, a comparison unit, a first resistor array, a second resistor array, and a resistor array control unit is provided. The signal processing unit receives an input differential signal and generates an output differential signal. The comparison unit detects and determines a first DC output voltage and a second DC output voltage of the output differential signal and generates a DC offset signal. First ends of the first resistor array and the second resistor array are respectively coupled to a first input terminal and a second input terminal of the signal processing unit. The resistor array control unit adjusts resistances of the first and the second resistor array according to the DC offset signal and a bit code sequence until the DC offset signal enters a transient state, so as to calibrate a DC offset voltage in the output differential signal.

Abstract: An automatic frequency calibration circuit and an automatic frequency calibration method for a fractional-N frequency synthesizer are provided. In a calibration mode, a state machine adjusts a fractional part and an integer part of a division ratio of a frequency divider unit according to a required precision. A first and a second frequency detecting units detect a reference frequency and an output frequency of the frequency divider unit, respectively. A judging interval unit defines at least one judging period in a total comparison time. A comparator compares the outputs of the first and the second frequency detecting units and outputs a comparison result at the judging period. Wherein, the state machine changes the capacitor configuration of a voltage-controlled oscillator when the comparison result shows that the reference frequency does not match the output frequency of the frequency divider unit.

Abstract: A low noise amplifier including an amplifier kernel circuit and a DC bias unit is provided. The amplifier kernel circuit is used for receiving a single input signal or a differential input signal so as to output a differential output signal. The DC bias unit is coupled to the amplifier kernel circuit, and is used for processing a signal source to generate the single input signal or the differential input signal according to its circuit configuration.

Abstract: An automatic frequency calibration circuit and an automatic frequency calibration method for a fractional-N frequency synthesizer are provided. In a calibration mode, a state machine adjusts a fractional part and an integer part of a division ratio of a frequency divider unit according to a required precision. A first and a second frequency detecting units detect a reference frequency and an output frequency of the frequency divider unit, respectively. A judging interval unit defines at least one judging period in a total comparison time. A comparator compares the outputs of the first and the second frequency detecting units and outputs a comparison result at the judging period. Wherein, the state machine changes the capacitor configuration of a voltage-controlled oscillator when the comparison result shows that the reference frequency does not match the output frequency of the frequency divider unit.

Abstract: A low noise amplifier including an amplifier kernel circuit and a DC bias unit is provided. The amplifier kernel circuit is used for receiving a single input signal or a differential input signal so as to output a differential output signal. The DC bias unit is coupled to the amplifier kernel circuit, and is used for processing a signal source to generate the single input signal or the differential input signal according to its circuit configuration.

Abstract: A low-noise amplifier circuit includes a MOS transistor in a common gate amplifier configuration. A single-ended input is at a source of the MOS transistor. A resonant cavity filter circuit is coupled to a gate of the MOS transistor.

Abstract: A device for voltage-noise rejection and fast start-up is provided. It comprises a low-pass filter connected to a voltage source, a voltage-controlled switch connected in parallel with the low-pass filter, and an auxiliary start-up element connected to a DC-only voltage output. By using a transistor operating in the triode region and a capacitor with suitable capacitance, it is suitable for integration to form a low-frequency low-pass pole to suppress the noise in the reference current. The auxiliary start-up element overcomes the large turn on time caused by the low frequency low-pass pole. As there is no static current during normal operation, the power consumption for the device is low.

Abstract: An operational amplifier includes a first stage and a second stage, the first stage for receiving two input signals and the second stage being coupled to the first stage, wherein the second stage includes a first part with a first output of the operational amplifier, and a second part with a second output of the operational amplifier. A method includes providing a first current to the first part of the second stage, and providing a second current to the second part of the second stage. The method further includes adjusting the first current based on a current consumption of the first part of the second stage, and adjusting the second current based on a current consumption of the second part of the second stage, wherein the sum of the first current and the second current is substantially constant.

Abstract: A frequency synthesizer includes: a fractional-N synthesizer configured to provide, in a locked condition, an output signal with an output frequency based on an input signal with a reference frequency, the fractional-N synthesizer including a charge pump outputting a current to be calibrated; a lock detector coupled to the fractional-N synthesizer to detect the locked condition, the lock detector being configured to send a first signal indicating the detection; a calibration component coupled to the lock detector and the fractional-N synthesizer, the calibration component being configured to provide a second signal to calibrate the current after receiving the first signal, based on a voltage sampled from the fractional-N synthesizer; and a current source array coupled to the calibration component and the fractional N synthesizer, the current source array being configured to calibrate the current based on the second signal.

Abstract: A variable gain amplifier to convert an amplifier input voltage to an amplifier output voltage, the variable gain amplifier includes: a plurality of cascode amplifiers coupled in series; a plurality of switching transistor pair circuits coupled in series; and a bias circuit coupled to provide bias voltages to each of the plurality of cascode amplifiers; wherein each of the switching transistor pair circuits is further coupled between two consecutive ones of the cascode amplifiers; a first one of the cascode amplifiers is configured to receive the amplifier input voltage; and a last one of the cascode amplifiers is configured to provide the amplifier output voltage.

Abstract: A low-noise amplifier circuit to convert a single-ended input into a dual-ended output includes an input transconductance stage circuit, including a first MOS transistor coupled in parallel with a second MOS transistor; a current buffer circuit, including a third MOS transistor coupled in parallel with a fourth MOS transistor; each of the first, second, third, and fourth transistors having a body, gate, source, and drain; the input transconductance stage circuit and the current buffer circuit being cascode coupled, forming a cascode amplifier configuration; the single-ended input being at the source of one of the first and second transistors in the input transconductance stage circuit; the dual-ended output being a differential output across the drain of the third transistor and the drain of the fourth transistor; the first and second transistors of the input transconductance stage circuit being cross-coupled, wherein the body of the first transistor is coupled to the source of the second transistor, and the

Abstract: A transconductor to convert an input voltage to an output current, includes: a primary transconductance stage to provide the output current from the input voltage and a driving current; an adaptive transconductance stage coupled in series with the primary transconductance stage to generate the driving current from the input voltage; and a bias circuit coupled to provide a primary bias voltage to the primary transconductance stage and an adaptive bias voltage to the adaptive transconductance stage.

Abstract: A calibration apparatus includes an RC integrator circuit. The calibration apparatus further includes a bandwidth setting controller to provide a bandwidth setting code indicating a reference bandwidth value for calibration of the RC integrator circuit and a capacitance code generator, coupled to the RC integrator circuit, to generate a capacitance code to adjust a capacitance of the RC integrator circuit using the bandwidth setting code and a current capacitance value of the RC integrator circuit.

Abstract: A variable gain amplifier to convert an amplifier input voltage to an amplifier output voltage, the variable gain amplifier includes: a plurality of cascode amplifiers coupled in series; a plurality of switching transistor pair circuits coupled in series; and a bias circuit coupled to provide bias voltages to each of the plurality of cascode amplifiers; wherein each of the switching transistor pair circuits is further coupled between two consecutive ones of the cascode amplifiers; a first one of the cascode amplifiers is configured to receive the amplifier input voltage; and a last one of the cascode amplifiers is configured to provide the amplifier output voltage.

Abstract: A low-noise amplifier circuit to convert a single-ended input into a dual-ended output includes an input transconductance stage circuit, including a first MOS transistor coupled in parallel with a second MOS transistor; a current buffer circuit, including a third MOS transistor coupled in parallel with a fourth MOS transistor; each of the first, second, third, and fourth transistors having a body, gate, source, and drain; the input transconductance stage circuit and the current buffer circuit being cascode coupled, forming a cascode amplifier configuration; the single-ended input being at the source of one of the first and second transistors in the input transconductance stage circuit; the dual-ended output being a differential output across the drain of the third transistor and the drain of the fourth transistor; the first and second transistors of the input transconductance stage circuit being cross-coupled, wherein the body of the first transistor is coupled to the source of the second transistor, and the

Abstract: A low-noise amplifier circuit includes a MOS transistor in a common gate amplifier configuration. A single-ended input is at a source of the MOS transistor. A resonant cavity filter circuit is coupled to a gate of the MOS transistor.