Abstract: The present disclosure provides resistive random-access memory (RRAM) devices and methods for making the same. An RRAM device may include a first electrode, a second electrode including a conductive material, and a switching oxide layer fabricated between the first electrode and the second electrode. The switching oxide layer is deuterium treated and contains deuterium. In some embodiments, the switching oxide layer includes a base oxide and a dopant oxide that is more chemically stable than the base oxide. The first electrode includes a non-reactive material that is not reactive to the base oxide or the dopant oxide. In some embodiments, the base oxide is Ta2O5, and the dopant oxide is Al2O3, SiO2, ZrO2, Sc2O3, or Y2O3. The RRAM device may further include an interface layer fabricated between the switching oxide layer and the second electrode. The interface layer is deuterium treated.

Abstract: The present disclosure provides resistive random-access memory (RRAM) devices and methods for making the same. An RRAM device may include a first electrode, a second electrode including a conductive material, and a switching oxide layer fabricated between the first electrode and the second electrode. The switching oxide layer includes a base oxide and a dopant oxide that is more chemically stable than the base oxide. The first electrode includes a non-reactive material that is not reactive to the base oxide or the dopant oxide. In some embodiments, the base oxide is Ta2O5, and the dopant oxide is Al2O3, SiO2, ZrO2, Sc2O3, or Y2O3.

Abstract: The present disclosure provides resistive random-access memory (RRAM) devices and methods for making the same. An RRAM device may include a first electrode, a second electrode comprising ruthenium, and a switching oxide layer fabricated between the first electrode and the second electrode. The first electrode includes at least one of palladium, titanium nitride, or tantalum nitride. The switching oxide layer comprises at least one transition metal oxide. In some embodiments, the RRAM device further includes an interface layer positioned between the switching oxide layer and the second electrode and/or an interface layer positioned between the first electrode and the switching oxide layer.

Abstract: The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) for a crossbar circuit. A processing device may perform a programming process to program the conductance of a resistive random-access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a random telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise-reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

Abstract: A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x?2.0, and wherein y?2.5. The interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Abstract: A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x?2.0, and wherein y?2.5. The interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Abstract: An apparatus including a plurality of resistive random-access memory (RRAM) devices is provided. The RRAM devices are fabricated on a single substrate in some embodiments. The apparatus includes an interconnect layer fabricated on the substrate. A first RRAM device of the RRAM devices includes a first bottom electrode, a first top electrode; and a first filament-forming layer fabricated between the first bottom electrode and the first top electrode. A second RRAM device of the RRAM devices includes a second bottom electrode, a second top electrode, and a second filament-forming layer fabricated between the second bottom electrode and the second top electrode. The first bottom electrode and the second bottom electrode are fabricated on multiple metallic pads or metallic vias of the interconnect layer. The first filament-forming layer and the second filament-forming layer include different switching oxides.

Abstract: A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

Abstract: A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide layer comprising at least one transition metal oxide; a top electrode, and an interface between the switching oxide layer and the top electrode. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x?2.0, and wherein y?2.5. The interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The forming-free RRAM device may be switched to multiple resistance levels without a forming process.

Abstract: An apparatus including a CMOS-compatible resistive random-access memory (RRAM) devices is provided. The apparatus includes a transistor; one or more first interconnect layers fabricated on the transistor; an RRAM device fabricated on the one or more first interconnect layers; and one or more second interconnect layers fabricated on the RRAM device. The RRAM device includes: a bottom electrode; a switching oxide layer including a transition metal oxide; a top electrode; and one or more interface layer including a material that is more chemically stable than the transition metal oxide. In some embodiments, one or more diffusion barriers and/or adhesion layers are fabricated between the RRAM device and the first interconnect layers and/or between the RRAM device and the second interconnect layers.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. The first electrode includes a metal nitride layer containing a metal nitride and a metal layer fabricated on the metal nitride layer. The metal layer includes a metal that is not reactive to the at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The metal layer includes a layer of a noble metal, such as platinum, palladium, iridium, or ruthenium, etc.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating an RRAM device includes: fabricating a first bottom electrode and a second bottom electrode on a substrate; fabricating a first isolation layer on the substrate, the first bottom electrode, and the second bottom electrode; fabricating a via in the first isolation layer to expose a portion of the first bottom electrode; fabricating a switching oxide layer on the first isolation layer and the exposed portion of the first bottom electrode; and fabricating a filament-forming layer by etching a portion of the switching oxide layer that extends beyond the via. The portion of the switching oxide layer does not contact the exposed portion of the first bottom electrode. A top electrode is fabricated on the filament-forming layer. A top metal interconnect may be fabricated on the top electrode and a second isolation layer.

Abstract: The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a switching oxide layer positioned between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and/or tantalum nitride. The first electrode does not include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: A method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover caps on the sacrificial layer such that the cover caps respectively enclose the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of active units of the device wafer so as to form an active part suspended in each of the active units; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.

Abstract: A micro-electromechanical system microstructure includes: a substrate adapted to support an electrode thereon; a suspension mechanism supported on the substrate; and a movable active part adapted to cooperate with the electrode to define a capacitor therebetween, and suspended on the substrate through the suspension mechanism so as to be movable to and fro relative to the substrate and the electrode. The suspension mechanism includes at least one supporting frame that protrudes from and that cooperates with an outer surface of the substrate to define a frame space therebetween, and at least one cantilever beam interconnecting the supporting frame and the active part.

Abstract: A method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover caps on the sacrificial layer such that the cover caps respectively enclose the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of active units of the device wafer so as to form an active part suspended in each of the active units; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.