Abstract: An active matrix substrate is provided. The active matrix substrate includes a substrate, a plurality of scan lines disposed on the substrate, a plurality of data lines disposed on the substrate, a plurality of pixel units disposed on the substrate and a dielectric layer disposed on the substrate. The pixel units are electrically connected with the corresponding scan lines and data lines. Each pixel unit includes an active device and a pixel electrode electrically connected with the active device, such a pixel electrode includes at least a first slit. The dielectric layer covers the first slit, and the dielectric layer includes a plurality of second slits for exposing a part of each of the pixel electrodes.

Abstract: A liquid crystal display device and a forming method of the electrode plate are disclosed. The forming method of the electrode plate includes providing one or more bottom plane electrodes, one or more conductive layers and a dielectric layer, floating the bottom plane electrodes, electrically connecting the conductive layers and an electrode of a thin film transistor, positioning the dielectric layer between the bottom plane electrodes and the conductive layers, utilizing the conductive layers, the dielectric layer and the bottom plane electrodes to form a coupling capacitor, and adjusting the capacitance of the coupling capacitor to control the voltage on the bottom plane electrodes. Therefore, the liquid crystal display device makes every sub-pixel have a predetermined voltage-transmittance characteristic curve by controlling the voltage on the bottom plane electrodes.

Abstract: An array substrate capable for a liquid crystal display (LCD). A pixel electrode is disposed in a pixel region of a substrate, which comprises at least one slit. A storage capacitor is disposed between the substrate and the pixel electrode, which comprises a bottom electrode, a capacitor dielectric layer, and a top electrode. The bottom electrode is disposed in the pixel region, creating an overlap region with the slit. The capacitor dielectric layer and the top electrode are successively disposed on the bottom electrode, in which the top electrode comprises at least one recess region to partially expose the overlap region.

Abstract: A display capable of providing 2D and/or 3D images. The display comprises a liquid crystal display device and a self-emissive display device. The self-emissive display device is disposed on the rear of the liquid crystal display device, in which the liquid crystal display device provides a first image and the self-emissive display device a second image and a backlight source. One of the first and second images comprises a parallax barrier pattern for forming a three-dimensional (3D) image, and the other is a 2D image.

Abstract: An LCD device having adjustable viewing angles includes a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate has a first common electrode. The second substrate has a pixel electrode, a second common electrode, and an insulating layer formed between the pixel electrode and the second common electrode. While in a narrow viewing angle mode of the LCD device, a driving voltage is applied to the pixel electrode, the first common electrode is grounded, and the second common electrode is floating. While in a wide viewing angle mode of the LCD device, a driving voltage is applied to the pixel electrode, the second common electrode is grounded, and the first common electrode is floating.

Abstract: A pixel structure of a liquid crystal display (LCD) panel including an upper substrate, a lower substrate, an LC layer, and a common electrode layer is provided. The LC layer is interposed between the upper substrate and the lower substrate. The common electrode layer is formed on a lower surface of the upper substrate and has at least a separating structure to divide the common electrode layer into several zones including a first zone and a second zone applied with different common voltage levels within a pixel structure.

Abstract: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied to said pixel electrode, the first electrode and the common electrode have a higher absolute voltage difference than the second electrode and the common electrode. The third electrode and the common electrode have the lowest absolute voltage difference.

Abstract: A multi-layer printed circuit board includes at least a ground plane for providing a ground level, at least a signal plane having a plurality of trace regions for transmitting signals, at least a power plane region having a plurality of power blocks for individually providing a plurality of voltage levels, and at least a via for electrically connecting the trace regions with the power plane region or the ground plane. Two adjacent power blocks with different voltage levels are separated by an insulating line. The insulating line has a plurality of first insulating sectors, and a plurality of second insulating sectors for connecting two adjacent first insulating sectors when an included angle of the adjacent first insulating sectors is greater than a predetermined value.

Abstract: A liquid crystal display (LCD) panel using a slanted electric field to control the inclination direction of liquid crystal (LC) molecules and a method of fabricating the same are disclosed. The asymmetrical bumps made of material with high dielectric constant are formed on the lower substrate, thereby improving the displaying quality of the LCD panel. After a potential difference is applied to the substrates of the LCD, a slanted electric field is generated due to the formation of asymmetrical bumps, so as to control the inclination direction of LC molecules. Also, the electrode layer could be formed over the asymmetric bumps, or formed between the asymmetric bumps and the bottom substrate.

Abstract: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied to said pixel electrode, the first electrode and the common electrode have a higher absolute voltage difference than the second electrode and the common electrode. The third electrode and the common electrode have the lowest absolute voltage difference.

Abstract: A pixel array for an LCD panel includes a plurality of pixel units scattered in an array manner. Each pixel unit includes a common electrode, a liquid crystal layer and a pixel electrode, wherein a plurality of pixel patterns are fabricated on the common electrode and the pixel electrode, and wherein the pixel patterns of adjacent two of the pixel electrodes are symmetric.

Abstract: A multi-domain vertical alignment liquid crystal display (MVA LCD) has a plurality of pixel electrodes for defining a plurality of pixel units. The pixel units are disposed in matrix arrangement, and each of them has a first electrode, a second electrode, and a third electrode. When a voltage is applied to said pixel electrode, the first electrode and the common electrode have a higher absolute voltage difference than the second electrode and the common electrode. The third electrode and the common electrode have the lowest absolute voltage difference.

Abstract: A multi-layer printed circuit board includes at least a ground plane for providing a ground level, at least a signal plane having a plurality of trace regions for transmitting signals, at least a power plane region having a plurality of power blocks for individually providing a plurality of voltage levels, and at least a via for electrically connecting the trace regions with the power plane region or the ground plane. Two adjacent power blocks with different voltage levels are separated by an insulating line. The insulating line has a plurality of first insulating sectors, and a plurality of second insulating sectors for connecting two adjacent first insulating sectors when an included angle of the adjacent first insulating sectors is greater than a predetermined value.

Abstract: The present invention is an apparatus and method for performing a Gaussian Minimum Shift Keying baseband modulation based on a reference phase to be simplified. The invention mainly comprises: a memory unit storing a plurality of parameters and their corresponding tabular data of a low pass Gaussian filter, the parameters and their corresponding tabular data being simplified in advance; the low pass filter being used for reducing the bandwidth of the apparatus and increasing the utilization of the bandwidth; and a processing unit based on the input digital data and the tabular data in the memory unit to generate the digital in-phase signal In and the digital quadrature-phase signal Qn.

Abstract: The present invention is an apparatus and method for performing a &pgr;/4-DQPSK baseband modulation based on a signal mapping to be simplified. The apparatus mainly comprises a memory unit and as processing unit. The memory unit stores a plurality of parameters and their corresponding tabular data of a low pass filter, and the parameters and their corresponding tabular data are simplified in advance. The low pass filter is used for reducing the bandwidth of the apparatus and increasing the utilization of the bandwidth. The processing, unit bases on the input digital data and the tabular data in the memory unit to generate a digital in-phase signal In and a digital quadrature-phase signal Qn.

Abstract: An improvement on the phase-locked loop (PLL) circuit, in which an amplifier is disposed at the modulating signal input end of the PLL, and the output end of the amplifier is connected in series to a resistor and an inductor, followed by a resistor connected to a higher DC bias as well as a variable capacitance diode connected to ground. In such a way, the variable capacitance diode is under the higher bias and thus has a smaller capacitance change, while having its Q-value property opposite to the resonance curve formed by the crystal unit of an oscillator which is associated in parallel with the variable capacitance diode, thereby forming in a good compensation for the linearity of the circuit architecture and achieving an ideal frequency deviation and a reduced distortion caused by the modulation.