Abstract: A signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a first output signal according to a gain; a first magnitude detector receiving the first output signal and generating a first magnitude signal; a first adder for subtracting the first magnitude signal from a reference value, thereby generating a first sampling signal; and a first weighting integrator receiving the first input signal, the second input signal and the first sampling signal, and generating the first integrated signal to control the gain of the first gain-adjustable amplifier.

Abstract: A signal processing apparatus receiving a first input signal and the first input signal being directly used as a first output signal. The signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a gain-adjusted first input signal according to a gain; a first adder for subtracting the gain-adjusted first input signal from the second input signal, thereby generating a second output signal; and a weighting correlator receiving the first output signal and the second output signal, and generating the first integrated signal to control the gain.

Abstract: A signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a gain-adjusted first input signal according to a first gain; a first adder for subtracting the gain-adjusted first input signal from the second input signal, thereby generating a second output signal; a second gain-adjustable amplifier receiving the second input signal and generating a gain-adjusted second input signal according to a second gain; a second adder for subtracting the gain-adjusted second input signal from the first input signal, thereby generating a first output signal; and a weighting correlator receiving the first output signal and the second output signal, and generating the first integrated signal to control the first gain and the second gain.

Abstract: A signal processing apparatus receiving a first input signal and the first input signal being directly used as a first output signal. The signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a gain-adjusted first input signal according to a gain; a first adder for subtracting the gain-adjusted first input signal from the second input signal, thereby generating a second output signal; and a weighting correlator receiving the first output signal and the second output signal, and generating the first integrated signal to control the gain.

Abstract: A signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a gain-adjusted first input signal according to a first gain; a first adder for subtracting the gain-adjusted first input signal from the second input signal, thereby generating a second output signal; a second gain-adjustable amplifier receiving the second input signal and generating a gain-adjusted second input signal according to a second gain; a second adder for subtracting the gain-adjusted second input signal from the first input signal, thereby generating a first output signal; and a weighting correlator receiving the first output signal and the second output signal, and generating the first integrated signal to control the first gain and the second gain.

Abstract: A signal processing apparatus comprising: a first gain-adjustable amplifier receiving the first input signal and generating a first output signal according to a gain; a first magnitude detector receiving the first output signal and generating a first magnitude signal; a first adder for subtracting the first magnitude signal from a reference value, thereby generating a first sampling signal; and a first weighting integrator receiving the first input signal, the second input signal and the first sampling signal, and generating the first integrated signal to control the gain of the first gain-adjustable amplifier.

Abstract: A signal processing apparatus includes an adder and a weighting integrator. The adder receives a first input signal and an integrated signal, and generates a first output signal. The first output signal is obtained by subtracting the integrated signal from the first input signal. The weighting integrator receives the first output signal, and generates the integrated signal. The weighting integrator includes a weighting function generator, a multiplier, and an accumulator. The weighting function generator receives the first output signal. When the first output signal crosses a zero crossing point, the weighting function generator generates a weighting function. The multiplier performs a multiplication on the weighting function and the first output signal. The accumulator is connected to the multiplier for accumulating the product of the weighting function and the first output signal, thereby generating the integrated signal.

Abstract: A DC offset cancellation circuit is provided. A first DC current and a first sensing current are superposed with each other to generate a first superposed current. A second DC current and a second sensing current are superposed with each other to generate a second superposed current. The first superposed current is converted into a first voltage signal. The second superposed current is converted into a second voltage signal. After the first voltage signal and the second voltage signal are received by a differential amplifier, an output signal is generated. The output signal is processed into a DC value. The DC value is converted into a DC current signal. The superposing unit generates the first DC current and the second DC current according to the DC current signal, so that the first superposed current and the second superposed current have the same DC offset.

Abstract: A battery status indicating method for an electronic device is provided. The battery module is pluggable into the electronic device. When a residual electric quantity of the battery module is lower than a threshold electric quantity, the battery module stops outputting a battery voltage. The battery status indicating method includes steps of judging whether the battery module is in a plugged status or an unplugged status according to the battery voltage, periodically charging the battery module in a first time interval of a fixed cycle if the battery module is in the unplugged status, and judging whether the battery module is switched to the unplugged status according to a change of the battery voltage if the battery module is in the plugged status.

Abstract: A DC offset cancellation circuit is provided. A first DC current and a first sensing current are superposed with each other to generate a first superposed current. A second DC current and a second sensing current are superposed with each other to generate a second superposed current. The first superposed current is converted into a first voltage signal. The second superposed current is converted into a second voltage signal. After the first voltage signal and the second voltage signal are received by a differential amplifier, an output signal is generated. The output signal is processed into a DC value. The DC value is converted into a DC current signal. The superposing unit generates the first DC current and the second DC current according to the DC current signal, so that the first superposed current and the second superposed current have the same DC offset.

Abstract: A signal processing apparatus includes an adder and a weighting integrator. The adder receives a first input signal and an integrated signal, and generates a first output signal. The first output signal is obtained by subtracting the integrated signal from the first input signal. The weighting integrator receives the first output signal, and generates the integrated signal. The weighting integrator includes a weighting function generator, a multiplier, and an accumulator. The weighting function generator receives the first output signal. When the first output signal crosses a zero crossing point, the weighting function generator generates a weighting function. The multiplier performs a multiplication on the weighting function and the first output signal. The accumulator is connected to the multiplier for accumulating the product of the weighting function and the first output signal, thereby generating the integrated signal.

Abstract: A battery status indicating method for an electronic device is provided. The battery module is pluggable into the electronic device. When a residual electric quantity of the battery module is lower than a threshold electric quantity, the battery module stops outputting a battery voltage. The battery status indicating method includes steps of judging whether the battery module is in a plugged status or an unplugged status according to the battery voltage, periodically charging the battery module in a first time interval of a fixed cycle if the battery module is in the unplugged status, and judging whether the battery module is switched to the unplugged status according to a change of the battery voltage if the battery module is in the plugged status.

Abstract: An automatic configuration system for automatically configuring a connecting interface of a node device in a network is provided. The connecting interface of the node device includes a first pair of connectors and a second pair of connectors. The automatic configuration system includes a switching unit, a first analog circuit unit, a second analog circuit unit and a detecting unit. The detecting unit is used to detect whether a first computed result or a second computed result outputted from the first analog circuit unit or the second analog circuit unit involves signals transmitted from another node device in the network, and accordingly generate a detected result to allow the switching unit to execute a switching operation and selectively connect the transmitting unit to the first or second pair of connectors, so as to ensure that data can be transmitted or received reliably in the network.

Abstract: A receiver with baseline wander compensation is applicable to a digital communication system. The receiver includes an Analog-to-Digital Converter (ADC), a slicer, a threshold value detector, a gain controller, a baseline wander compensator, a delay circuit, an analog gain stage, and a digital gain stage. The baseline wander compensator is used to perform an operation and a filtering process on a voltage obtained prior to processing by the slicer and a voltage after the processing so as to obtain a baseline wander voltage value for compensation and control. The threshold value detector and the gain controller dynamically produce control signals of analog gain and digital gain. The analog gain stage compensates degrading of communication signals passing through transmission channels in an analog gain manner. The delay circuit is used to compensate the delay of the conversion performed by the ADC. The digital gain stage compensates insufficiency of the analog gain.

Abstract: This invention presents a novel receiver architecture for full-duplex multi-level PAM systems. The receiver employs an Analog-to-Digital Converter (ADC) that has a sample rate flexibly specified as (Ns+1)/Ns baud rate where Ns is an integer equal or greater than 1. A fractional-spaced echo canceller is used to cancel the echo at the ADC output. The use of a fractional sampling rate higher than the baud rate also enables the timing recovery function be implemented in the digital domain and hence eliminates the need of using the complex analog phase selection circuit. The receiver is also capable of fast, blind start-up by use of a decision feedback equalizer with unity main tap and a soft level slicer. The timing phase can be optimally located using a derivative channel estimator.

Abstract: Decoding systems and methods for deciding a compensated signal are provided. The decoding system comprises a slicer, a compensator, and a selector. The slicer is used for generating a pre-decision symbol. The compensator is used for determining a predetermined range of the compensated signal. The selector is used for deciding the compensated signal in response to the pre-decision symbol, the predetermined range and a set of previous symbols. The predetermined range is to limit the calculation range of the compensated signal so that the required hardware is reduced.

Abstract: An automatic configuration system and method is provided. A detecting unit is used to detect whether a signal indicating link establishment appears at a first connector or a second connector, which serves as a receiving terminal of a node device, and accordingly generate a detecting result. Thus, according to the detecting result, an automatic configuration control unit controls a switching unit to execute a corresponding switching operation and sequentially configure the first connector and the second connector, so as to ensure that data can be transmitted and received reliably in the communication network and to save power.

Abstract: An automatic configuration system for automatically configuring a connecting interface of a node device in a network is provided. The connecting interface of the node device includes a first pair of connectors and a second pair of connectors. The automatic configuration system includes a switching unit, a first analog circuit unit, a second analog circuit unit and a detecting unit. The detecting unit is used to detect whether a first computed result or a second computed result outputted from the first analog circuit unit or the second analog circuit unit involves signals transmitted from another node device in the network, and accordingly generate a detected result to allow the switching unit to execute a switching operation and selectively connect the transmitting unit to the first or second pair of connectors, so as to ensure that data can be transmitted or received reliably in the network.

Abstract: This invention presents a novel receiver architecture for full-duplex multi-level PAM systems. The receiver employs an Analog-to-Digital Converter (ADC) that has a sample rate flexibly specified as (Ns+1)/Ns baud rate where Ns is an integer equal or greater than 1. A fractional-spaced echo canceller is used to cancel the echo at the ADC output. The use of a fractional sampling rate higher than the baud rate also enables the timing recovery function be implemented in the digital domain and hence eliminates the need of using the complex analog phase selection circuit. The receiver is also capable of fast, blind start-up by use of a decision feedback equalizer with unity main tap and a soft level slicer. The timing phase can be optimally located using a derivative channel estimator.

Abstract: An active hybrid circuit for a full duplex channel generates a duplicated voltage at the current output stage to reduce the energy of the transmitter transmitted to the receiver. The active hybrid circuit cancels the energy of the transmitter transmitted to the receiver when it is operated in a full duplex channel with high-speed transmission. The active hybrid circuit for full a duplex channel comprises a transmit digital-to-analog converter for generating an analog transmit signal, a receive analog-to-digital converter for receiving an analog receive signal, a duplicated voltage digital-to-analog converter for generating a corresponding duplicated voltage according to the analog transmit signal of the transmit digital-to-analog converter, and a plurality of signal combiners for subtracting the duplicated voltage from the analog transmit signal to cancel the influence of analog transmit signal to the analog receive signal.