Abstract: The present invention proposes a new asymmetric-lightly-doped drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added efficiency (PAE). The PAE is also improved by 16% at 10-dBm output power and 2.4 GHz. These significant improvements of RF power performance by this new MOS transistor make the RF-CMOS system-on-chip design a step further. Index Terms—Lightly-doped-drain (LDD), metal oxide semiconductor field effect transistor (MOSFET), metal oxide semiconductor (MOS) transistor, radio frequency (RF) power transistor.

Abstract: A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.

Abstract: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

Abstract: A yield patrolling system, which monitors production yield of a manufacturing line, has at least one product measurement and test device. The product measurement and test device measures yield determining parameters of product at completion of process steps executed by equipment within the manufacturing line. The system further has a test database in communication with the product measurement and test device to receive and retain the measured yield determining parameters. A statistical calculator is in communication with the test database to receive the measured yield determining parameters. The statistical calculator then calculates from the measured yield determining parameters production yield statistics indicating an amount of the product being fabricated on the manufacturing line.

Abstract: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

Abstract: A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.

Abstract: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

Abstract: A new method of preventing passivation keyhole damage and resist extrusion by a resist crosslinking mechanism is described. Semiconductor device structures are formed in and on a semiconductor substrate and covered by an insulating layer. Metal lines are formed overlying the insulating layer wherein there is a gap between two of the metal lines. A passivation layer is deposited overlying the metal lines. A negative tone photoresist material is coated over the passivation layer. The photoresist is exposed to light through a mask wherein the mask is clear overlying the metal lines in an active area and wherein the mask is opaque overlying a metal line in a bonding pad area where a bonding pad is to be formed. The portion of the negative tone photoresist underlying the clear mask is exposed to light whereby crosslinks are formed within the exposed photoresist and wherein the portion of the photoresist underlying the opaque mask is unexposed.

Abstract: A method for attenuating within a microelectronics fabrication a standing wave photoexposure of a photoresist layer formed upon a reflective layer, and a microelectronics fabrication employed within the method. To practice the methods there is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a reflective layer. There is then formed upon the reflective layer a birefringent material layer. The birefringent material layer attenuates a standing wave photoexposure of a photoresist layer subsequently formed upon the birefringent material layer, where the photoresist layer is subsequently photoexposed with an actinic photoexposure radiation beam.

Abstract: A low cost, fast method for evaluating the effects of lens heating in a step and repeat projection system is disclosed. The first step is to form a series of photoresist images on a single substrate in the same way as would be done during normal stepping and repeating. The first few images, located centrally, will be produced by a cool lens. As more images are generated, the lens gradually heats up so that the final few images, which are placed alongside the `cool` images, will be produced by a hot lens. Critical dimension bars are present in all image fields (at diagonally opposite corners and in the center), their size in the developed photoresist being an indication of the extent to which the focal plane has drifted. This is then used to compute correction factors for the manufacturer's scaling constants and/or to evaluate the extent, if any, of curvature of field in the projected images.

Abstract: The present invention discloses a method for forming a pattern for stepper focus which can be monitored by overlay measurements such that a focal plane can be advantageously and accurately determined without human reading errors that are normally observed in conventional methods. The method for forming a stepper focus pattern for determining a focus error can be carried out by using an inner box and an outer box alignment marks and determining the shift in the center point of the two boxes as the overlay error.

Abstract: A method for attenuating within a microelectronics fabrication a standing wave photoexposure of a photoresist layer formed upon a reflective layer, and a microelectronics fabrication employed within the method. To practice the method, there is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a reflective layer. There is then formed upon the reflective layer a birefringent material layer. The birefringent material layer attenuates a standing wave photoexposure of a photoresist layer subsequently formed upon the birefringent material layer, where the photoresist layer is subsequently photoexposed with an actinic photoexposure radiation beam.