Abstract: A memory control system has an SDRAM device, a memory controller, a loading monitoring unit and a memory physical module. The SDRAM device has a plurality of SDRAM cells for storing data. The loading monitoring unit detects workload of a memory interface of the SDRAM device. The memory controller switches an operation condition of the memory system from a first condition to a second condition when the detected workload satisfies at least one predetermined criterion. The memory physical module is coupled between the SDRAM device and the memory controller and has an interface timing calibration circuit configured to adjust timing of signals of the memory interface such that the signals are adjusted in best timing location and data are captured with a great timing margin.

Abstract: A multi-functional eyeglasses includes two lenses and an eyeglass frame including two supporting rods and two lens frames; each lens frame being installed with a respective one of the lenses. The multi-functional eyeglasses has a processor, a memory and a display. The eyeglasses can be installed with a receiver and a transmitter, a GPS positioning system, a Bluetooth system, a camera, a sound control system, a TV circuit, a scanner, a clinical thermometer, a thermometer, a batter, a solar energy chip, USP plugs, switching set. This, the functions of eyeglasses are expanded extremely so as to provide great convenience to users.

Abstract: A pair of personalized eyeglasses comprises two lenses; a lens frame having a lens retaining portion for retaining the two lenses and two supporting rods extending from two sides of the lens retaining portion; and at least one texture area; texts on the texture area being on the lens frame or the lenses, or concaved into a surface of the lens frame or the lenses; or protruded from a surface of the lens frame or the lenses. The texts are at least one of names of users, address of users, ID numbers of users, phone numbers of users, birthdays of users, and data about the user's personal profiles; or the texts are about greeting, alerting, congratulations, anniversaries; or the data shown on the texture area is a section of article.

Abstract: In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.

Abstract: A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master.

Abstract: A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.

Abstract: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

Abstract: In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.

Abstract: An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.

Abstract: A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.

Abstract: A pre-fetch control method comprises the following steps. First, after a data request for M-bytes request data sent from a cache controller is received, a determination is made on whether the M-bytes request data are found in the pre-fetch buffer. Then, a further determination is made on whether a combined access control is enabled if the M-bytes request data are not found in the pre-fetch buffer. If the combined access is not enabled, a data request for the M-bytes request data is sent out to an external unit. If the combined access control is enabled, a data request for the M-bytes request data and n*M-bytes extra data is sent out to an external unit. The n*M-bytes extra data is stored in the pre-fetch buffer.

Abstract: A system capable of dynamically arranging coprocessor number, which uses a coprocessor instruction to be an instruction between a master processor and one or more coprocessors. The system includes plural coprocessors and a master processor. The plural coprocessors help the master processor to perform additional operations. The master processor executes plural instructions for data operations and applies the coprocessor instruction for data access and communication between the master processor and the coprocessors. The coprocessor instructions have at least one rearranged coprocessor instruction field and one main instruction opcode field each. The rearranged coprocessor instruction field has fields of coprocessor number, coprocessor opcode number and coprocessor register, or fields of coprocessor number and coprocessor register.

Abstract: A processor and method capable of executing instruction sets with different lengths is disclosed. The instruction sets include at least an N-bit instruction set and a 2N-bit instruction set. The 2N-bit instruction set includes an instruction set switch instruction (ISSI-2N-N). The N-bit instruction set includes an instruction set switch instruction (ISSI-N-2N). When the ISSI-2N-N is fetched, an instruction decoding device and an instruction executing device are switched to an N-bit mode. When the ISSI-N-2N is fetched, the instruction decoding device and the instruction executing device are switched to a 2N-bit mode. In the N-bit mode, the instruction decoding device decodes a fetched 2N bit word as two N-bit instructions and the instruction executing device executes the two decoded N-bit instructions. In the 2N-bit mode, the instruction decoding device decodes a fetched 2N bit word as a 2N-bit instruction and the instruction executing device executes the decoded 2N-bit instruction.

Abstract: A device for coupling a battery to an electric appliance including two magnetic plates, one of the magnetic plates having an opening for engagement with a center electrode of the battery, the other magnetic plate attractable to the case electrode of the battery, and a wire for electrically coupling the magnetic plates to the electric appliance in order to energize the electric appliance.

Abstract: An instrument for measuring angles, vertical line or horizontal line includes a square casing having two axial lines crossing at a center of the casing and having a colored liquid filled in the casing, and a rotating disc rotatably mounted on the casing, in which the rotating disc is formed with an upper half circle portion radially formed with a plurality of angular graduations in terms of degrees, and formed with a lower half circle portion having two vertical columns parallelly formed below a diametrical line dividing the two half circle portions, and at least a reference line linked between any two horizontal graduations respectively formed in the two vertical columns, whereby upon a rotation of the disc to parallel the reference line to a liquid level of the colored liquid, an angle can be obtained by matching the angular graduation with any one axial line when the casing is laid on or coincided with a plane to be measured.