Patents by Inventor Ming Chuan You

Ming Chuan You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH VOLTAGE INTEGRATED CIRCUIT TESTING INTERFACE ASSEMBLY
    Publication number: 20210231729
    Abstract: An integrated circuit testing assembly that includes: (i) a first slug configured to contact a first surface of a first set of pins of an integrated circuit; (ii) a second slug configured to contact a second surface of the first set of pins of the integrated circuit; (iii) a third slug configured to contact a first surface of a second set of pins of the integrated circuit; and (iv) a fourth slug configured to contact a second surface of the second set of pins of the integrated circuit.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 29, 2021
    Inventors: Ming-Chuan You, Andrew Patrick Couch, Phillip Marcus Blitz, Xinkun Huang, Chi-Tsung Lee, Roy Deidrick Solomon, Enis Tuncer
  • High-voltage isolator testing
    Patent number: 10871514
    Abstract: A handler for holding an electronic device during high voltage testing includes conductive lead guides for shorting leads on one side of the isolator together and connectors connecting the lead guides to conductors.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 22, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chi-Tsung Lee, Ming-Chuan You, Chien-Lin Wu, David Anthony Graham, Andrew Patrick Couch
  • HIGH-VOLTAGE ISOLATOR TESTING
    Publication number: 20170328947
    Abstract: A handler for holding an electronic device during high voltage testing includes conductive lead guides for shorting leads on one side of the isolator together and connectors connecting the lead guides to conductors.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 16, 2017
    Inventors: Chi-Tsung Lee, Ming-Chuan You, Chien-Lin Wu, David Anthony Graham, Andrew Patrick Couch
  • Automatic selective retest for multi-site testers
    Patent number: 7650255
    Abstract: A method of multi-site testing a batch of semiconductor units using a multi-site automated tester (100). The tester (300) includes a handler (320) coupled to a contactor (330) including a first plurality of contact sites. The method includes the step of loading the first plurality of units into the first plurality of contact sites (201). The first plurality of units are simultaneously tested (202) using a test program to determine bin information for each of the first plurality of units, wherein the bin information defines each of the first plurality units as being a passed unit or a reject unit. The passed units are offloaded from respective contact sites of the first plurality of contact sites to create vacant contact sites (203), while keeping the reject unit(s) at respective contact sites of the first plurality of contact sites. Untested units from the batch are then loaded to fill the vacant contact sites (204).
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: January 19, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Chi Tsung Lee, Sheng Pin Chen, Ming Chuan You, Shou Ping Hsu
  • AUTOMATIC SELECTIVE RETEST FOR MULTI-SITE TESTERS
    Publication number: 20090276175
    Abstract: A method of multi-site testing a batch of semiconductor units using a multi-site automated tester (100). The tester (300) includes a handler (320) coupled to a contactor (330) including a first plurality of contact sites. The method includes the step of loading the first plurality of units into the first plurality of contact sites (201). The first plurality of units are simultaneously tested (202) using a test program to determine bin information for each of the first plurality of units, wherein the bin information defines each of the first plurality units as being a passed unit or a reject unit. The passed units are offloaded from respective contact sites of the first plurality of contact sites to create vacant contact sites (203), while keeping the reject unit(s) at respective contact sites of the first plurality of contact sites. Untested units from the batch are then loaded to fill the vacant contact sites (204).
    Type: Application
    Filed: May 2, 2008
    Publication date: November 5, 2009
    Inventors: Chi Tsung Lee, Sheng Pin Chen, Ming Chuan You, Shou Ping Hsu