Patents by Inventor Ming-Chun ChenHsu

Ming-Chun ChenHsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electrostatic discharge protection device
    Patent number: 10720420
    Abstract: Provided is an electrostatic discharge protection device including a first work area and a second work area. The first work area is configured to form a face-to-face connected diode string. The first work area includes a plurality of first sub-work areas. Each of the first sub-work areas includes a first doped region of a first conductivity type disposed in a substrate, a second doped region of a second conductivity type disposed in the substrate and surrounding the first doped region, and a third doped region of the second conductivity type disposed below the second doped region. The second work area is configured to form at least one diode. The second work area includes at least one second sub-work area. The second sub-work area includes a fourth doped region of the second conductivity type disposed in the substrate. Besides, the fourth doped region is electrically connected to the first doped region.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 21, 2020
    Assignee: uPI Semiconductor Corp.
    Inventors: Ming-Chun ChenHsu, Chih-Hao Chen
  • ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    Publication number: 20190371786
    Abstract: Provided is an electrostatic discharge protection device including a first work area and a second work area. The first work area is configured to form a face-to-face connected diode string. The first work area includes a plurality of first sub-work areas. Each of the first sub-work areas includes a first doped region of a first conductivity type disposed in a substrate, a second doped region of a second conductivity type disposed in the substrate and surrounding the first doped region, and a third doped region of the second conductivity type disposed below the second doped region. The second work area is configured to form at least one diode. The second work area includes at least one second sub-work area. The second sub-work area includes a fourth doped region of the second conductivity type disposed in the substrate. Besides, the fourth doped region is electrically connected to the first doped region.
    Type: Application
    Filed: November 5, 2018
    Publication date: December 5, 2019
    Applicant: uPI Semiconductor Corp.
    Inventors: Ming-Chun ChenHsu, Chih-Hao Chen