Abstract: A plastic light-folding element includes an incident surface, an exit surface, at least one reflective surface, at least one connecting surface and at least one gate vestige structure. The incident surface is configured to lead an imaging light enter the plastic light-folding element. The exit surface is configured to lead the imaging light exit the plastic light-folding element. The reflective surface is configured to fold the imaging light. The connecting surface is connected to the incident surface, the exit surface and the reflective surface. The gate vestige structure is disposed on the connecting surface. At least one of the incident surface, the exit surface and the reflective surface includes an optical portion and an arc step structure, the arc step structure is disposed on a periphery of the optical portion, and an arc is formed by the arc step structure centered on the optical portion.

Abstract: A method of slicing wafers from a monocrystalline semiconductor ingot includes attaching a circumferential edge of the ingot to a bond beam and positioning sacrificial disks adjacent longitudinal end faces of the ingot. One sacrificial disk is positioned adjacent each of the longitudinal end faces. The method also includes connecting the bond beam to a wire saw that includes a wire web and performing a slicing operation on the ingot by operating the wire saw to drive the wire web and move the bond beam and the ingot in a movement direction towards the wire web to slice the wafers from the ingot.

Abstract: A system for slicing wafers from a monocrystalline semiconductor ingot includes a wire saw, a bond beam, the monocrystalline semiconductor ingot, and two sacrificial disks. The wire saw includes a wire web and wire guides operable to drive the wire web during a slicing operation. The bond beam is connected to the wire saw. The wire saw is operable to move the bond beam in a movement direction towards the wire web during the slicing operation to slice the wafers from the ingot. The ingot includes longitudinal end faces and a circumferential edge extending between the longitudinal end faces. The ingot is attached to the bond beam along the circumferential edge. One sacrificial disk is positioned adjacent each of the longitudinal end faces of the ingot to inhibit uncontrolled breakage of the wafers during the slicing operation.

Abstract: An induction heating cooker and a control circuit therefor are provided. The cooker includes a switch element and an inductive coil, which is coupled between a power voltage and a first terminal of the switch element. A second terminal of the switch element is coupled to a common voltage. The control circuit includes first and second comparators and a pulse generator. The first comparator receives voltages of two terminals of the inductive coil and thus outputs a trigger signal. The second comparator receives a reference voltage and a voltage of the first terminal of the switch element, and enables a fading signal when the voltage of the first terminal is higher than the reference voltage. When the trigger signal is enabled, the pulse generator outputs a pulse to control the switch element. When the fading signal is enabled, the pulse generator reduces a pulse width of the pulse.

Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.

Abstract: An induction heating cooker includes a switch element and an inductive coil, which is coupled between a power voltage and a first terminal of the switch element. A second terminal of the switch element is coupled to a common voltage. A control circuit for controlling the inducting heating cooker includes first and second comparators and a pulse generator. The first comparator receives voltages of two terminals of the inductive coil and thus outputs a trigger signal. The second comparator receives a reference voltage and a voltage of the first terminal of the switch element, and enables a fading signal when the voltage of the first terminal is higher than the reference voltage. When the trigger signal is enabled, the pulse generator outputs a pulse to control the switch element. When the fading signal is enabled, the pulse generator reduces a pulse width of the pulse.

Abstract: An induction heating cooker and a control circuit therefor are provided. The cooker includes a switch element and an inductive coil, which is coupled between a power voltage and a first terminal of the switch element. A second terminal of the switch element is coupled to a common voltage. The control circuit includes first and second comparators and a pulse generator. The first comparator receives voltages of two terminals of the inductive coil and thus outputs a trigger signal. The second comparator receives a reference voltage and a voltage of the first terminal of the switch element, and enables a fading signal when the voltage of the first terminal is higher than the reference voltage. When the trigger signal is enabled, the pulse generator outputs a pulse to control the switch element. When the fading signal is enabled, the pulse generator reduces a pulse width of the pulse.

Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.

Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.

Abstract: A power noise immunity circuit includes a unidirectional device and a switch both connected between a power input terminal and a power output terminal, and a noise detector to control the switch. The power input terminal is for being connected to an external voltage source, and the power output terminal is for being connected to the circuit of an IC. The switch is normally closed and is opened by the noise detector if the noise detector detects power noise at the power input terminal. The power noise immunity circuit thus prevents the IC from power breakdown and provides a stable voltage thereto.

Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.

Abstract: The invention relates to an induction heating cooker and a control circuit therefor. The cooker includes a switch element and an inductive coil, which is coupled between a power voltage and a first terminal of the switch element. A second terminal of the switch element is coupled to a common voltage. The control circuit includes first and second comparators and a pulse generator. The first comparator receives voltages of two terminals of the inductive coil and thus outputs a trigger signal. The second comparator receives a reference voltage and a voltage of the first terminal of the switch element, and enables a fading signal when the voltage of the first terminal is higher than the reference voltage. When the trigger signal is enabled, the pulse generator outputs a pulse to control the switch element. When the fading signal is enabled, the pulse generator reduces a pulse width of the pulse.

Abstract: A method, device, and system for positioning a brush of a wafer cleaning system. In the method, device, and system one or more light sources are positioned to generate one or more light beams across a plane. One or more light detectors are positioned to detect when the light beams are interrupted by the brush as it advances toward the plane.

Abstract: A method for measuring a thickness of a photolithography element, such as a pellicle, includes projecting a light beam from a first side of the pellicle and at a plane above a first surface of the pellicle, projecting the light beam from the first side of the pellicle and at a plane corresponding to a plane of the pellicle, and projecting the light beam from the first side of the pellicle and at a plane below a second surface of the pellicle. The light beam can be projected from a laser light source. The light beams are projected at different media above and below the pellicle. The light beams pass through the first side of the different media and exit at a second side opposite to the first side at different intensities. The light beam may not pass through the pellicle if the light beam is incident to an opaque pellicle frame, and thus has minimal intensity at the second side.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate; the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Most of the Cu2+ ions will accumulate in and around defective contacts or vias in the semiconductor surface making these defective contacts or vias readily identifiable.

Abstract: A method for forming a critical dimension scanning electron microscope calibration standard and standard formed are disclosed. In the method, a plurality of metal lines, i.e. formed of a suitable metal such as W, Pt, Au, Ta or Ti, for use as critical dimension SEM calibration is formed by a focused ion beam technique to produce straight, narrow lines with an edge roughness of less than 30 nm in a 0.5 &mgr;m length. The plurality of metal lines has a line width uniformity of less than 20 nm in a length of 20 &mgr;m.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate, the dc current ionizes the CUSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Defects in the glassification surface will absorb most of the Cu2+ ions, concentrations of Cu2 ions will therefore from around these defects.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate; the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Most of the Cu2+ ions will accumulate in and around defective contacts or vias in the semiconductor surface making these defective contacts or vias readily identifiable.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate; the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Most of the Cu2+ ions will accumulate in and around defective contacts or vias in the semiconductor surface making these defective contacts or vias readily identifiable.

Abstract: A cathode-anode apparatus is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The wafer under test and the copper plate are immersed in a CuSO4—H2O solution. A positive dc voltage is applied to the copper plate, the dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will diffuse to the wafer surface. Defects in the glassification surface will absorb most of the Cu2+ ions, concentrations of Cu2+ ions will therefore from around these defects.