Abstract: A display device including at least two light source modules and a display control substrate is provided. Each of the at least two light source substrates has a first surface and a second surface opposite to each other and includes a plurality of light emitting elements and a plurality of connection pads. The light emitting elements are located on the second surface, and the connection pads are located on the first surface and are electrically connected to the light emitting elements. The display control substrate includes a back plate and a plurality of control elements. The control elements are located on the back plate, part of the control elements are electrically connected to the connection pads to drive and control the light emitting elements, and the second surface of each of the at least two light source substrates forms a part of a display surface of the display device.

Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.

Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.

Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.

Abstract: The present invention discloses an FFT-based ADC calibration system able to solve the problems of capacitor mismatch and finite Op-Amp open loop gain, which result in that the radix of the gain of each stage is not exactly equal to 2. The present invention uses an FFT processor to calculate the real radix of each stage and uses a digital method to generate new digital outputs. As the present invention can compensate the finite gain of Op-Amp, the specification of Op-Amp is not so critical in designing ADC. Therefore, the low-gain Op-Amp can be used to reduce the power consumption of ADC. Further, the FFT-based calibration technology can considerably promote the performance of ADC.

Abstract: The present invention discloses an FFT-based ADC calibration system able to solve the problems of capacitor mismatch and finite Op-Amp open loop gain, which result in that the radix of the gain of each stage is not exactly equal to 2. The present invention uses an FFT processor to calculate the real radix of each stage and uses a digital method to generate new digital outputs. As the present invention can compensate the finite gain of Op-Amp, the specification of Op-Amp is not so critical in designing ADC. Therefore, the low-gain Op-Amp can be used to reduce the power consumption of ADC. Further, the FFT-based calibration technology can considerably promote the performance of ADC.