Abstract: In a method for managing video conference bandwidth, original video images with a predetermined quantity are acquired from a video sent from a client device. The video sent from the client device is compressed according to a default video compression parameter. The compressed video images corresponding to the original video images are acquired. A current network bandwidth is detected and compared with the data bandwidth of the compressed video. A video quality assessed value of the compressed video is calculated in event the current network bandwidth is larger than the data bandwidth of the compressed video. The default video compression parameter will be regulated and the video will be recompressed until the video quality assessed value of the compressed video is within the scope of predetermined quality requirement while the video quality assessed value of the compressed video is beyond the scope of a predetermined quality requirement.

Abstract: In a method for managing video conference bandwidth, original video images with a predetermined quantity are acquired from a video sent from a client device. The video sent from the client device is compressed according to a default video compression parameter. The compressed video images corresponding to the original video images are acquired. A current network bandwidth is detected and compared with the data bandwidth of the compressed video. A video quality assessed value of the compressed video is calculated in event the current network bandwidth is larger than the data bandwidth of the compressed video. The default video compression parameter will be regulated and the video will be recompressed until the video quality assessed value of the compressed video is within the scope of predetermined quality requirement while the video quality assessed value of the compressed video is beyond the scope of a predetermined quality requirement.

Abstract: A resource sharing method for sharing user interfaces and multimedia files uses a video conferencing system which includes at least one computer, a local video terminal, a multipoint control unit (MCU), and at least one remote video terminal. The resource method includes steps where the at least one computer analyzes the format of the multimedia files and determines whether or not the local video terminal can support the format(s) of the multimedia files. The at least one computer may transmit the multimedia file(s) to the local video terminal and a multipoint control unit (MCU) and to the at least one remote video terminal through the MCU.

Abstract: A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations.

Abstract: A resource sharing method for sharing user interfaces and multimedia files uses a video conferencing system which includes at least one computer, a local video terminal, a multipoint control unit (MCU), and at least one remote video terminal. The resource method includes steps where the at least one computer analyzes the format of the multimedia files and determines whether or not the local video terminal can support the format(s) of the multimedia files. The at least one computer may transmit the multimedia file(s) to the local video terminal and a multipoint control unit (MCU) and to the at least one remote video terminal through the MCU.

Abstract: A discrete cosine transformation circuit comprising a pipeline with a memory stage and an arithmetic stage. The arithmetic stage comprises first and second arithmetic logic units (ALU). Each of the ALUs receives from the memory a set of image data, performs a first calculation on the set of image data and outputs calculation result thereof in a first clock cycle. A path in the circuit directs the result to the memory stage, such that at least one ALU can selectively receive the result from the path in a clock cycle subsequent to the first clock cycle.

Abstract: A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations.

Abstract: A discrete cosine transformation circuit comprising a pipeline with a memory stage and an arithmetic stage. The arithmetic stage comprises first and second arithmetic logic units (ALU). Each of the ALUs receives from the memory a set of image data, performs a first calculation on the set of image data and outputs calculation result thereof in a first clock cycle. A path in the circuit directs the result to the memory stage, such that at least one ALU can selectively receive the result from the path in a clock cycle subsequent to the first clock cycle.

Abstract: A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus arbiter and an external memory controller. The signal relay device facilitates data transfer of large groups of read/write commands between the main masters and the external memory controller.

Abstract: A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus arbiter and an external memory controller. The signal relay device facilitates data transfer of large groups of read/write commands between the main masters and the external memory controller.