Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: An image sensor module includes a sensing surface, a filter element and a first anti-reflective microstructure, wherein the filter element faces towards the sensing surface, and the first anti-reflective microstructure is disposed on the sensing surface. The filter element includes a substrate, an optical deposition layer structure and an optical coating layer, wherein the optical deposition layer structure is disposed on a side of the substrate away from the sensing surface, and the optical coating layer and the optical deposition layer structure are correspondingly disposed on a side of the substrate facing towards the sensing surface. The optical deposition layer structure is multilayer. An air layer is formed between the first anti-reflective microstructure and the filter element, and the first anti-reflective microstructure and the air layer partially overlap at a direction vertical to the sensing surface.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: An testing method includes following operations: generating, by a signal generator, a multi-tone signal; transmitting, by the signal generator, the multi-tone signal to an input terminal of an under-test device; measuring, by a spectrum analyzer, the input terminal of the under-test device and an output terminal of the under-test device to acquire a plurality of input ripple intensities corresponding to a plurality of frequencies and acquire a plurality of output ripple intensities corresponding to the frequencies; and generating, by a control device, a plurality of power supply rejection ratios corresponding to the frequencies according to the input ripple intensities and the output ripple intensities.

Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Abstract: The application discloses a measuring system and associated method for measuring phases of IMD3 signals generated from a power amplifier. The method includes: performing a phase estimation process, including a plurality of sub-processes, wherein each sub-process includes: generating a first main signal, a second main signal, a first adjustable signal, wherein frequencies of the first main signal, the second main signal, the first adjustable signal are f1, f2, 2f1-f2; and correspondingly measuring a first power at frequency of 2f1-f2; and estimating a phase of the IMD3 signal at frequency of 2f1-f2 caused by the first main signal and the second main signal passing through the power amplifier according to a plurality of first powers obtained from the plurality of sub-processes; wherein in each sub-process, a phase of the first adjustable signal is different from that of other sub-processes.

Abstract: A signal adjustment device includes a frequency adjustment circuit, a filter circuit, and a power estimation circuit. The frequency adjustment circuit is configured to receive a two-tone signal from a signal generator and to generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is configured to filter the first signal, in order to generate a second signal. The power estimation circuit is configured to detect a power of an intermodulation distortion from the third order signal component, which is associated with the two-tone signal, in the second signal, and to adjust at least one of the first coefficient and the second coefficient according to the power, in order to reduce the power.

Abstract: An testing method includes following operations: generating, by a signal generator, a multi-tone signal; transmitting, by the signal generator, the multi-tone signal to an input terminal of an under-test device; measuring, by a spectrum analyzer, the input terminal of the under-test device and an output terminal of the under-test device to acquire a plurality of input ripple intensities corresponding to a plurality of frequencies and acquire a plurality of output ripple intensities corresponding to the frequencies; and generating, by a control device, a plurality of power supply rejection ratios corresponding to the frequencies according to the input ripple intensities and the output ripple intensities.

Abstract: A signal adjustment device includes a frequency adjustment circuit, a filter circuit, and a power estimation circuit. The frequency adjustment circuit is configured to receive a two-tone signal from a signal generator and to generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is configured to filter the first signal, in order to generate a second signal. The power estimation circuit is configured to detect a power of an intermodulation distortion from the third order signal component, which is associated with the two-tone signal, in the second signal, and to adjust at least one of the first coefficient and the second coefficient according to the power, in order to reduce the power.

Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.

Abstract: A signal compensation device comprises a first filter circuit, for processing a broadband signal, to generate a first analog time-domain signal; a second filter circuit, for processing the broadband signal, to generate a second analog time-domain signal; a first transform circuit, for transforming the first analog time-domain signal to a first digital time-domain signal; a second transform circuit, for transforming the second analog time-domain signal to a second digital time-domain signal; a third transform circuit, for transforming the first digital time-domain signal to a first frequency-domain signal; a fourth transform circuit, for transforming the second digital time-domain signal to a second frequency-domain signal; and a processing circuit, for generating a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal.

Abstract: A signal compensation device comprises a first filter circuit, for processing a broadband signal, to generate a first analog time-domain signal; a second filter circuit, for processing the broadband signal, to generate a second analog time-domain signal; a first transform circuit, for transforming the first analog time-domain signal to a first digital time-domain signal; a second transform circuit, for transforming the second analog time-domain signal to a second digital time-domain signal; a third transform circuit, for transforming the first digital time-domain signal to a first frequency-domain signal; a fourth transform circuit, for transforming the second digital time-domain signal to a second frequency-domain signal; and a processing circuit, for generating a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal.

Abstract: A receiving circuit includes: a first receiving terminal for receiving a RF signal; a second receiving terminal for receiving an external oscillating signal generated by an external oscillator; a low-noise amplifier coupled with the first receiving terminal and the second receiving terminal and utilized for generating an output signal; a first switch element positioned between the second receiving terminal and the low-noise amplifier; an in-phase signal processing circuit for generating an in-phase detection signal based on the output signal; an quadrature signal processing circuit for generating an quadrature detection signal based on the output signal; and a calibration circuit for controlling the first switch element and capable of performing an I/Q mismatch calibration operation according to the in-phase detection signal and the quadrature detection signal when the first switch element is turned on.

Abstract: A receiving circuit includes: a first receiving terminal for receiving a RF signal; a second receiving terminal for receiving an external oscillating signal generated by an external oscillator; a low-noise amplifier coupled with the first receiving terminal and the second receiving terminal and utilized for generating an output signal; a first switch element positioned between the second receiving terminal and the low-noise amplifier; an in-phase signal processing circuit for generating an in-phase detection signal based on the output signal; an quadrature signal processing circuit for generating an quadrature detection signal based on the output signal; and a calibration circuit for controlling the first switch element and capable of performing an I/Q mismatch calibration operation according to the in-phase detection signal and the quadrature detection signal when the first switch element is turned on.

Abstract: The present invention discloses a wireless signal receiving device and method capable of receiving three or more signals of different central frequencies. An embodiment of said device comprises: a receiving circuit operable to generate a reception signal according to a wireless signal including a first, second, and third wireless signals of different central frequencies; a mixer operable to generate a mixing signal by processing the reception signal according to an oscillation clock in which the mixing signal includes a first, second and third intermediate-frequency (IF) signals and the central frequency of the third IF signal is higher than the other two; and a digital signal generating circuit operable to generate a first, second and third digital signals by processing the first, second and third IF signals according to a sampling frequency in which the sampling frequency is lower than two times the maximum frequency of the third IF signal.

Abstract: A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed.

Abstract: The present invention discloses a wireless signal receiving device and method capable of receiving three or more signals of different central frequencies. An embodiment of said device comprises: a receiving circuit operable to generate a reception signal according to a wireless signal including a first, second, and third wireless signals of different central frequencies; a mixer operable to generate a mixing signal by processing the reception signal according to an oscillation clock in which the mixing signal includes a first, second and third intermediate-frequency (IF) signals and the central frequency of the third IF signal is higher than the other two; and a digital signal generating circuit operable to generate a first, second and third digital signals by processing the first, second and third IF signals according to a sampling frequency in which the sampling frequency is lower than two times the maximum frequency of the third IF signal.

Abstract: An oscillating frequency drift detecting method, which comprises: receiving an oscillating signal with an oscillating frequency, wherein the oscillating signal is generated by a crystal oscillator; generating a self-mixing signal according to the oscillating signal; obtaining a self-mixing frequency of a maximum power of the self-mixing signal in a specific frequency range; and computing a frequency drift of the oscillating frequency, according to the self-mixing frequency of the maximum power, and the oscillating frequency.

Abstract: A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed.

Abstract: The present invention discloses a method for adjusting a tunable compensation filter within a communication device. The method includes the following steps: generating at least a detecting signal according to at least a pole of the tunable compensation filter; generating a transmitted signal according to the detecting signal; receiving the transmitted signal via a loop switch; generating a filtered signal by filtering the transmitted signal; generating a received signal by compensating the filtered signal; generating at least an indicating signal by comparing the detecting signal with the received signal; and determining whether to adjust at least a coefficient of the tunable compensation filter or not according to the indicating signal.