Patents by Inventor Ming-Chung Huang
Ming-Chung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961919Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.Type: GrantFiled: March 21, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
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Publication number: 20240120315Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.Type: ApplicationFiled: February 15, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Tze-Chiang Huang, Yun-Han Lee, Lee-Chung Lu
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Patent number: 11956261Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.Type: GrantFiled: May 12, 2021Date of Patent: April 9, 2024Assignee: Acer Cyber Security IncorporatedInventors: Chiung-Ying Huang, Yi-Chung Tseng, Ming-Kung Sun, Tung-Lin Tsai
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Publication number: 20240111430Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.Type: ApplicationFiled: November 9, 2022Publication date: April 4, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Yi-Chung Chen, Ming-Chien Huang
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Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Publication number: 20240090340Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
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Patent number: 11711888Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.Type: GrantFiled: March 25, 2021Date of Patent: July 25, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Ming Huang, Ruey-Beei Wu, Shih-Hung Wang, Ting-Ying Wu, Ming-Chung Huang
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Publication number: 20230188228Abstract: The application discloses a measuring system and associated method for measuring phases of IMD3 signals generated from a power amplifier. The method includes: performing a phase estimation process, including a plurality of sub-processes, wherein each sub-process includes: generating a first main signal, a second main signal, a first adjustable signal, wherein frequencies of the first main signal, the second main signal, the first adjustable signal are f1, f2, 2f1-f2; and correspondingly measuring a first power at frequency of 2f1-f2; and estimating a phase of the IMD3 signal at frequency of 2f1-f2 caused by the first main signal and the second main signal passing through the power amplifier according to a plurality of first powers obtained from the plurality of sub-processes; wherein in each sub-process, a phase of the first adjustable signal is different from that of other sub-processes.Type: ApplicationFiled: December 5, 2022Publication date: June 15, 2023Inventors: MING-CHUNG HUANG, HSIANG-CHEN KUO
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Patent number: 11644491Abstract: A signal adjustment device includes a frequency adjustment circuit, a filter circuit, and a power estimation circuit. The frequency adjustment circuit is configured to receive a two-tone signal from a signal generator and to generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is configured to filter the first signal, in order to generate a second signal. The power estimation circuit is configured to detect a power of an intermodulation distortion from the third order signal component, which is associated with the two-tone signal, in the second signal, and to adjust at least one of the first coefficient and the second coefficient according to the power, in order to reduce the power.Type: GrantFiled: April 26, 2021Date of Patent: May 9, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ming-Chung Huang, I-Hua Tseng
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Publication number: 20230128364Abstract: An testing method includes following operations: generating, by a signal generator, a multi-tone signal; transmitting, by the signal generator, the multi-tone signal to an input terminal of an under-test device; measuring, by a spectrum analyzer, the input terminal of the under-test device and an output terminal of the under-test device to acquire a plurality of input ripple intensities corresponding to a plurality of frequencies and acquire a plurality of output ripple intensities corresponding to the frequencies; and generating, by a control device, a plurality of power supply rejection ratios corresponding to the frequencies according to the input ripple intensities and the output ripple intensities.Type: ApplicationFiled: September 30, 2022Publication date: April 27, 2023Inventors: Yi-Nan KUO, Ming-Chung HUANG
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Publication number: 20210389355Abstract: A signal adjustment device includes a frequency adjustment circuit, a filter circuit, and a power estimation circuit. The frequency adjustment circuit is configured to receive a two-tone signal from a signal generator and to generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is configured to filter the first signal, in order to generate a second signal. The power estimation circuit is configured to detect a power of an intermodulation distortion from the third order signal component, which is associated with the two-tone signal, in the second signal, and to adjust at least one of the first coefficient and the second coefficient according to the power, in order to reduce the power.Type: ApplicationFiled: April 26, 2021Publication date: December 16, 2021Inventors: MING-CHUNG HUANG, I-HUA TSENG
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Publication number: 20210368614Abstract: A power line structure includes a dielectric layer, a first conductive component, a second conductive component, and a third conductive component. The first conductive component is disposed at a first side of the dielectric layer. The second conductive component is disposed at the first side of the dielectric layer. The third conductive component is disposed at the first side of the dielectric layer and between the first conductive component and the second conductive component. Each of the voltage of the first conductive component and the second conductive component is equal to a ground voltage. The third conductive component is configured to receive a first power voltage.Type: ApplicationFiled: March 25, 2021Publication date: November 25, 2021Inventors: Chun-Ming HUANG, Ruey-Beei WU, Shih-Hung Wang, Ting-Ying WU, Ming-Chung Huang
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Patent number: 11184214Abstract: A signal compensation device comprises a first filter circuit, for processing a broadband signal, to generate a first analog time-domain signal; a second filter circuit, for processing the broadband signal, to generate a second analog time-domain signal; a first transform circuit, for transforming the first analog time-domain signal to a first digital time-domain signal; a second transform circuit, for transforming the second analog time-domain signal to a second digital time-domain signal; a third transform circuit, for transforming the first digital time-domain signal to a first frequency-domain signal; a fourth transform circuit, for transforming the second digital time-domain signal to a second frequency-domain signal; and a processing circuit, for generating a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal.Type: GrantFiled: January 2, 2020Date of Patent: November 23, 2021Assignee: Realtek Semiconductor Corp.Inventors: Ming-Chung Huang, Yuan-Shuo Chang, Tzu-Ming Kao
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Publication number: 20200403842Abstract: A signal compensation device comprises a first filter circuit, for processing a broadband signal, to generate a first analog time-domain signal; a second filter circuit, for processing the broadband signal, to generate a second analog time-domain signal; a first transform circuit, for transforming the first analog time-domain signal to a first digital time-domain signal; a second transform circuit, for transforming the second analog time-domain signal to a second digital time-domain signal; a third transform circuit, for transforming the first digital time-domain signal to a first frequency-domain signal; a fourth transform circuit, for transforming the second digital time-domain signal to a second frequency-domain signal; and a processing circuit, for generating a time-domain compensation response according to the first frequency-domain signal and the second frequency-domain signal.Type: ApplicationFiled: January 2, 2020Publication date: December 24, 2020Inventors: Ming-Chung Huang, Yuan-Shuo Chang, Tzu-Ming Kao
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Patent number: 9859997Abstract: A receiving circuit includes: a first receiving terminal for receiving a RF signal; a second receiving terminal for receiving an external oscillating signal generated by an external oscillator; a low-noise amplifier coupled with the first receiving terminal and the second receiving terminal and utilized for generating an output signal; a first switch element positioned between the second receiving terminal and the low-noise amplifier; an in-phase signal processing circuit for generating an in-phase detection signal based on the output signal; an quadrature signal processing circuit for generating an quadrature detection signal based on the output signal; and a calibration circuit for controlling the first switch element and capable of performing an I/Q mismatch calibration operation according to the in-phase detection signal and the quadrature detection signal when the first switch element is turned on.Type: GrantFiled: December 20, 2016Date of Patent: January 2, 2018Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ying-Hsi Lin, Ming-Chung Huang
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Publication number: 20170373770Abstract: A receiving circuit includes: a first receiving terminal for receiving a RF signal; a second receiving terminal for receiving an external oscillating signal generated by an external oscillator; a low-noise amplifier coupled with the first receiving terminal and the second receiving terminal and utilized for generating an output signal; a first switch element positioned between the second receiving terminal and the low-noise amplifier; an in-phase signal processing circuit for generating an in-phase detection signal based on the output signal; an quadrature signal processing circuit for generating an quadrature detection signal based on the output signal; and a calibration circuit for controlling the first switch element and capable of performing an I/Q mismatch calibration operation according to the in-phase detection signal and the quadrature detection signal when the first switch element is turned on.Type: ApplicationFiled: December 20, 2016Publication date: December 28, 2017Applicant: Realtek Semiconductor CorporationInventors: Ying-Hsi LIN, Ming-Chung HUANG
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Patent number: 9385760Abstract: The present invention discloses a wireless signal receiving device and method capable of receiving three or more signals of different central frequencies. An embodiment of said device comprises: a receiving circuit operable to generate a reception signal according to a wireless signal including a first, second, and third wireless signals of different central frequencies; a mixer operable to generate a mixing signal by processing the reception signal according to an oscillation clock in which the mixing signal includes a first, second and third intermediate-frequency (IF) signals and the central frequency of the third IF signal is higher than the other two; and a digital signal generating circuit operable to generate a first, second and third digital signals by processing the first, second and third IF signals according to a sampling frequency in which the sampling frequency is lower than two times the maximum frequency of the third IF signal.Type: GrantFiled: October 23, 2014Date of Patent: July 5, 2016Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Ming-Chung Huang
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Patent number: 9344096Abstract: A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed.Type: GrantFiled: July 30, 2014Date of Patent: May 17, 2016Assignee: Realtek Semiconductor Corp.Inventors: Ming-Chung Huang, Xinglong Liu
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Publication number: 20150133070Abstract: The present invention discloses a wireless signal receiving device and method capable of receiving three or more signals of different central frequencies. An embodiment of said device comprises: a receiving circuit operable to generate a reception signal according to a wireless signal including a first, second, and third wireless signals of different central frequencies; a mixer operable to generate a mixing signal by processing the reception signal according to an oscillation clock in which the mixing signal includes a first, second and third intermediate-frequency (IF) signals and the central frequency of the third IF signal is higher than the other two; and a digital signal generating circuit operable to generate a first, second and third digital signals by processing the first, second and third IF signals according to a sampling frequency in which the sampling frequency is lower than two times the maximum frequency of the third IF signal.Type: ApplicationFiled: October 23, 2014Publication date: May 14, 2015Inventor: Ming-Chung Huang
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Patent number: 9000855Abstract: An oscillating frequency drift detecting method, which comprises: receiving an oscillating signal with an oscillating frequency, wherein the oscillating signal is generated by a crystal oscillator; generating a self-mixing signal according to the oscillating signal; obtaining a self-mixing frequency of a maximum power of the self-mixing signal in a specific frequency range; and computing a frequency drift of the oscillating frequency, according to the self-mixing frequency of the maximum power, and the oscillating frequency.Type: GrantFiled: May 17, 2012Date of Patent: April 7, 2015Assignee: Realtek Semiconductor Corp.Inventor: Ming-Chung Huang