Abstract: The invention discloses a digital signature system. The digital signature system comprises an electronic device and a data storage device. The electronic device generates a specific data by executing a specific operation, and calculates the specific data via a hash algorithm to generate a hash data. The data storage device comprises a controller, a plurality of flash memories, and a data transmission interface. The electronic device transmits the hash data to the data storage device via the transmission interface. The controller comprises a firmware. The firmware reads an unclonable function, and generates a private key according to the unclonable function, and encrypts the hash data by the private key to obtain a digital signature. The data storage device transmits the digital signature to the electronic device via the transmission interface.

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.

Abstract: Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

Abstract: A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.

Abstract: A Sn—Ag bonding and a method thereof are revealed. By means of a bonding layer formed by tin and silver between wafers, the stress released by diffusion and bonding between tin(Sn) and silver(Ag) is larger than the stress released by diffusion and bonding of conventional gold-silver bonding. Moreover, a Sn—Ag bonding method of the present invention forms Sn—Ag bonding at low temperature and releases more stress so as to reduce thermal stress generated during wafer bonding effectively. And after wafer bonding, the high temperature processes can be performed.

Abstract: A Sn—Ag bonding and a method thereof are revealed. By means of a bonding layer formed by tin and silver between wafers, the stress released by diffusion and bonding between tin(Sn) and silver(Ag) is larger than the stress released by diffusion and bonding of conventional gold-silver bonding. Moreover, a Sn—Ag bonding method of the present invention forms Sn—Ag bonding at low temperature and releases more stress so as to reduce thermal stress generated during wafer bonding effectively. And after wafer bonding, the high temperature processes can be performed.

Abstract: A Sn—Ag bonding and a method thereof are revealed. By means of a bonding layer formed by tin and silver between wafers, the stress released by diffusion and bonding between tin (Sn) and silver (Ag) is larger than the stress released by diffusion and bonding of conventional gold-silver bonding. Moreover, a Sn—Ag bonding method of the present invention forms Sn—Ag bonding at low temperature and releases more stress so as to reduce thermal stress generated during wafer bonding effectively. And after wafer bonding, the high temperature processes can be performed.