Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A system for and a method of curing a material is provided. A material, such as an underfill material, is rotated during a curing process. The curing system may include a chamber, a holder to support one or more workpieces, and a rotating mechanism. The rotating mechanism rotates the workpieces during the curing process. The chamber may include one or more heat sources and fans, and may further include a controller. The curing process may include varying the rotation speed, continuously rotating, periodically rotating, or the like.

Abstract: Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder.

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.

Abstract: Disclosed herein is a system and method for mounting semiconductor packages by forming one or more interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a target package. Mounting the interconnect may comprise ultrasonically welding the interconnects to the mounting pads, and the interconnect may be mounted via a mounting node on the end of the interconnect, wherein the mounting node may be formed by an electric flame off process. The interconnects may be trimmed to one or more substantially uniform heights, optionally using a laser or contact-type trimming system, and the tails of the interconnects may be supported during trimming. A top package may be bonded on the trimmed ends of the interconnects. During mounting, a support plate may be used to support the package, and a mask maybe used during interconnect mounting.

Abstract: Methods and apparatus for alignment in a flip chip bonding. A method includes attaching an integrated circuit having connector terminals to a bonding arm, the bonding arm having a chuck for attaching the integrated circuit at the backside surface, the bonding arm having a plurality of CCD imagers mounted thereon; receiving a substrate having pads corresponding to the connector terminals; using the bonding arm, positioning the integrated circuit proximal to the substrate; aligning the integrated circuit connector terminals with the pads on the substrate using the CCD imagers on the bonding arm; positioning the connector terminals in contact with the pads on the substrate; and performing a solder reflow to attach the integrated circuit to the substrate. An apparatus includes a bonding arm with a chuck for carrying a component and CCD imagers mounted on the arm for alignment.

Abstract: Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits.

Abstract: Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder.

Abstract: Disclosed herein is a system and method for mounting semiconductor packages by forming one or more interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a target package. Mounting the interconnect may comprise ultrasonically welding the interconnects to the mounting pads, and the interconnect may be mounted via a mounting node on the end of the interconnect, wherein the mounting node may be formed by an electric flame off process. The interconnects may be trimmed to one or more substantially uniform heights, optionally using a laser or contact-type trimming system, and the tails of the interconnects may be supported during trimming. A top package may be bonded on the trimmed ends of the interconnects. During mounting, a support plate may be used to support the package, and a mask maybe used during interconnect mounting.

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die.

Abstract: A system for and a method of curing a material is provided. A material, such as an underfill material, is rotated during a curing process. The curing system may include a chamber, a holder to support one or more workpieces, and a rotating mechanism. The rotating mechanism rotates the workpieces during the curing process. The chamber may include one or more heat sources and fans, and may further include a controller. The curing process may include varying the rotation speed, continuously rotating, periodically rotating, or the like.

Abstract: Methods and apparatus for die assembly. A method includes forming a trench extending from an active surface of a semiconductor substrate comprising a plurality of integrated circuit dies having connector terminals extending from the active surface, the trench extending into, but not through, the semiconductor substrate; forming a protective layer overlying the active surface of the semiconductor substrate and the trench, and covering the lower portion of the connector terminals; opening a pre-dicing opening in the protective layer and within the trench; applying a tape over the active surface of the semiconductor wafer, the protective layer and the connector terminals; and performing an operation on a backside of the semiconductor substrate to remove material until the pre-dicing opening is exposed on the backside of the semiconductor wafer. An apparatus includes a semiconductor substrate with integrated circuits and a protective layer surrounding connector terminals of integrated circuits.

Abstract: Methods and apparatus for alignment in a flip chip bonding. A method includes attaching an integrated circuit having connector terminals to a bonding arm, the bonding arm having a chuck for attaching the integrated circuit at the backside surface, the bonding arm having a plurality of CCD imagers mounted thereon; receiving a substrate having pads corresponding to the connector terminals; using the bonding arm, positioning the integrated circuit proximal to the substrate; aligning the integrated circuit connector terminals with the pads on the substrate using the CCD imagers on the bonding arm; positioning the connector terminals in contact with the pads on the substrate; and performing a solder reflow to attach the integrated circuit to the substrate. An apparatus includes a bonding arm with a chuck for carrying a component and CCD imagers mounted on the arm for alignment.

Abstract: A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.

Abstract: A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.

Abstract: An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.

Abstract: A packaged semiconductor chip comprising an integrated circuit chip including a low-k dielectric layer and a chip substrate, wherein an edge of the integrated circuit chip has a first edge portion and a second edge portion. At least part of the first edge portion being across a same level as the low-k dielectric layer, and the first edge portion having been laser ablated to have a series of rounded recesses formed therein. The second edge portion being across a same level as at least part of the chip substrate, and the second edge portion having a different surface texture than that of the first edge portion. The packaged semiconductor chip also comprises a packaging substrate having the integrated circuit chip attached and a plurality of solder bumps electrically connecting between the packaging substrate and the integrated circuit chip.

Abstract: An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.