Patents by Inventor Ming Chung

Ming Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956261
    Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Acer Cyber Security Incorporated
    Inventors: Chiung-Ying Huang, Yi-Chung Tseng, Ming-Kung Sun, Tung-Lin Tsai
  • Publication number: 20240111430
    Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.
    Type: Application
    Filed: November 9, 2022
    Publication date: April 4, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yi-Chung Chen, Ming-Chien Huang
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240096811
    Abstract: The present disclosure provides a package structure and a method of manufacturing a package. The package structure includes a semiconductor die laterally encapsulated by an encapsulant, a redistribution structure and bumps. The redistribution structure is disposed on the semiconductor die and the encapsulant, and is electrically connected with the at least one semiconductor die. The bumps are disposed on the redistribution structure. The redistribution structure includes dielectric layers and metallic pattern layers sandwiched between the dielectric layers. The redistribution structure includes metallic pads on an outermost dielectric layer of the dielectric layers, and the outmost dielectric layer has undercut cavities beside the metallic pads.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chung Lu, Bo-Tao Chen, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
  • Publication number: 20240096849
    Abstract: A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chung Chang, Ming-Che Ho, Hung-Jui Kuo
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240086024
    Abstract: A method of creating a digital activity may include selecting an interactive digital design element to be added to the digital activity, the interactive digital design element configured to allow multiple users to interact with the interactive digital design element when deploying the digital activity. The method may include generating a data structure, the data structure representative of a repository into which data representative of user inputs are stored when interacting with the interactive digital design element when deployed. The method may include deploying the interactive digital design element in a visual space shared between the multiple users.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: Cole T. Rosenberg, Saurabh Sudhir Phadnis, Pinen Chen, Jarom Yan-Ming Chung, William Weilian Wang, Lucas Alexander Barnes
  • Publication number: 20240090340
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Publication number: 20240088154
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Publication number: 20240088691
    Abstract: The battery pack with the plurality of batteries is determined to have been fully charged and set in a stationary state, the discharge operation proceeds according to specified relationships of the voltage of each battery, a first predetermined voltage difference, and a discharge starting voltage, or the balance operation proceeds according to specified relationships of the voltage of each battery, the first predetermined voltage difference, a balance starting voltage and a second predetermined voltage difference.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: CHIH-YU CHUNG, Fong-Ming CHANG, TSUNG-NAN WU
  • Patent number: 11923870
    Abstract: A method for constructing an n-qubit fault tolerant encode for any k-qubit quantum gate M, in any given quantum code [n, k, C], comprising: choosing a number n?k of independent spinors Sr from the first stabilizer C and a first ordered set SC consists of the independent spinors Sr; choosing a number n?k of independent spinors ?r from a second stabilizer ? in the intrinsic coordinate and a second ordered set ?r consists of the independent spinors ?r consist; implementing an encoding Qen, wherein the encoding Qen converts the first ordered set SC to the second ordered set S?, wherein the encoding Qen is a sequential product provided by sequential operations of a number n?k of unitary operators Qr; wherein each of the unitary operator Qr is composed of a single s-rotation or a product of two s-rotations; and wherein the encoding Qen converts and maps the rth independent spinor Sr in the first ordered set SC to the rth independent spinor ?r in the second ordered set S? correspondingly; a fault tolerant action Û i
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: March 5, 2024
    Assignee: National Applied Research Laboratories
    Inventors: Zheng-Yao Su, Ming-Chung Tsai
  • Patent number: 11923350
    Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: March 5, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Ru Chen, Tzyy-Jang Tseng, Cheng-Chung Lo
  • Publication number: 20240071941
    Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Yun-Han Lee, Lee-Chung Lu
  • Patent number: 11908819
    Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Apple Inc.
    Inventors: Jun Chung Hsu, Chih-Ming Chung, Jun Zhai, Yifan Kao, Young Doo Jeon, Taegui Kim
  • Publication number: 20240033307
    Abstract: A method for enhancing sports performance and alleviating sarcopenia with a Streptococcus thermophiles ST7 fermentation product composition is disclosed. The administration of an effective amount of the Streptococcus thermophiles ST7 fermentation product composition to an individual in advance can increase the ATP content of the individual's muscle cells and lower indices related to fatigue and muscle damage, thereby enhancing the individual's sports performance and improving or preventing sarcopenia and its symptoms.
    Type: Application
    Filed: November 29, 2022
    Publication date: February 1, 2024
    Inventors: Wei-Jen CHEN, Tsung-Yin TANG, Ming-Chung TSENG, Yu-Shan WEI
  • Publication number: 20240014856
    Abstract: Presented herein are embodiments of a compact handheld integrated cabling assist (CHICA) device that has a form factor of a transceiver. In one or more embodiments, a CHICA embodiment may pair with a cabling assist application (CA-App) to guide a user with cabling decisions. A user may insert a transceiver (optic/DAC) in a mini-cage of the CHICA, wherein the CHICA reads the transceiver data, transmits the data to the CA-App to confirm that the transceiver meets the configuration requirements of the switch port. In one or more embodiments, a user may also interact with the CA-App to write data (e.g., EEPROM fields) to the transceiver by issuing commands via the CHICA device.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 11, 2024
    Applicant: DELL PRODUCTS L.P.
    Inventors: Padmanabhan NARAYANAN, Ming Chung CHOW, Vamshidhar VARRE
  • Publication number: 20230417520
    Abstract: In an embodiment, a photoinitiation apparatus includes: a set of illumination sources or elements configured for outputting optical energy; a body structure having a proximal body structure portion confining a proximal volume of explosive medium, an intermediate body structure portion confining an intermediate volume of explosive medium, and a distal body structure portion confining a distal volume of explosive medium, wherein the proximal volume of explosive medium is optically coupled to portions of the first volume of explosive medium, at least one of the proximal volume of explosive medium and the distal volume of explosive medium is a tertiary explosive medium, and (a) the body structure does not carry a primary explosive composition and does not carry a secondary explosive composition, and/or (b) each of the proximal, intermediate, and distal volumes of explosive media has an initiation sensitivity that is less than cyclotrimethylenetrinitramine (RDX) based explosive compositions.
    Type: Application
    Filed: February 20, 2023
    Publication date: December 28, 2023
    Inventors: David Olaf JOHNSON, Rodney Wayne APPLEBY, Richard John GOODRIDGE, Ming Chung LEE, Francisco SANCHEZ, Matthew Tolliver RAWLS
  • Publication number: 20230375813
    Abstract: A lens assembly includes a first lens group, a second lens group, and a third lens group, all of which are arranged in order from an object side to an image side along an optical axis. The first lens group is with positive refractive power and includes at least four lenses, among which the lens closest to the object side includes a convex surface facing the object side, and the lens closest to the image side includes a convex surface facing the image side. The second lens group is with negative refractive power and includes a 2-1 lens and a 2-2 lens, wherein the 2-2 lens includes a convex surface facing the image side. The third lens group is with negative refractive power and includes a 3-1 lens, wherein the 3-1 lens is a meniscus lens with negative refractive power.
    Type: Application
    Filed: December 23, 2022
    Publication date: November 23, 2023
    Inventor: Ming-Chung Chen
  • Publication number: 20230377746
    Abstract: A method for establishing robust prediction model is adapted for solving the problem that the conventional prediction model cannot generate stable and credible results with missing data. The method of the present invention includes the following steps: obtaining pre-established single-modality standard models respectively based on each type of modalities from samples; extracting modality sets each having the same modality types from the samples to establish corresponding multi-modalities standard models; extracting multiple combinations of the modality sets from the samples having complete modalities to be training data, wherein the multiple combinations of the modality sets can be classified into single-modality, multi-modalities and complete-modalities; inputting said training data into a to-be trained prediction model, and modifying the prediction model by said single-modality standard models and said multi-modalities standard models to obtain a well-trained prediction model.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 23, 2023
    Inventors: Yuh-Jyh JONG, Yuan-Han YANG, Ming-Chung CHOU, Shin-Mu TSENG, Jui-Hung HUNG, Hui-Min HSIEH, Shyh-Shin CHIOU
  • Publication number: 20230368144
    Abstract: An example method to facilitate online collaboration includes granting access to an editable collaboration space to multiple users. The method also includes dividing the users into subgroups including at least a first subgroup and a second subgroup. In addition, the method includes assigning the subgroups to different virtual breakout rooms in the editable collaboration space, including assigning users in the first subgroup to a first virtual breakout room and assigning users in the second subgroup to a second virtual breakout room that is different than the first virtual breakout room. Further, the method includes populating each virtual breakout room with common initial content obtained from a virtual common room, the common initial content being the same in each virtual breakout room.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Ryan J. Stringham, Jarom Yan-Ming Chung, Taylor Jessica Halversen, Karl Steven Baranov, Lindsey Whitefield Martin, Geoffrey Ryan Maddox, Sean P. McKenna, PinEn Chen, Vasu Nephi Chetty, Joseph Stack, Zachary Paul Luker