Patents by Inventor Ming-Dao Ker

Ming-Dao Ker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090040668
    Abstract: An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 12, 2009
    Inventors: Zi-Ping Chen, Ming-Dao Ker, Hsin-Chin Jiang
  • Patent number: 7304827
    Abstract: An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: December 4, 2007
    Inventors: Zi-Ping Chen, Ming-Dao Ker, Hsin-Chin Jiang
  • Publication number: 20040218322
    Abstract: An ESD protection circuit that protects a mixed-voltage input/output (I/O) buffer circuit in an integrated circuit is provided. The ESD protection circuit includes an ESD discharging circuit coupled to the I/O pad and ESD detection circuit coupled to the discharging circuit providing a means for detecting an ESD and triggering the discharging circuit to conduct the ESD to ground. The ESD discharging circuit comprises stacked NMOS transistors or a field oxide device (FOD). The protection circuit can also be used in an ESD protection circuit for a high-voltage-tolerant input pad or to protect multiple input pads and/or multiple I/O pads in an integrated circuit.
    Type: Application
    Filed: May 2, 2003
    Publication date: November 4, 2004
    Applicant: Industrial Technology Research Institute
    Inventors: Zi-Ping Chen, Ming-Dao Ker, Hsin-Chin Jiang