Abstract: Storage apparatus can support various memory units with different standards based on the method which drives the power control-and-switch circuit in the power management unit according to a control signal caused by the ID code of a memory unit to control the second booster for further increasing the level of the external voltage or control the second regulator for further regulating or decreasing the level of the external voltage.

Abstract: A flash memory device with a wear-levelining mechanism includes at least one flash memory, a hot list, a bitmap, a source pointer, and a controller. The controller obtains a physical memory block with high erase count through the hot list, an erase count of the physical memory block, and an overall average erase count of the flash memory device. The controller further finds out a physical memory block which stores static data through managing the bitmap and the source pointer. The controller moves the static data to the physical memory block with high erase count, and releases the physical memory block which stores the static data to avoid the physical memory block with high erase count being worn down increasingly more seriously.

Abstract: A control method for the memory system is suitable for a memory system to process the user data from a host. The control unit divides the address of the storage space of the host into a plurality of logical segments for accessing data. The memory system provides a storage space with a plurality of physical segments to access data. The control method comprises the following steps. Firstly, a master table is provided in the physical memory for recording the mapping relation between the addresses of the logical units and the addresses of the physical units. When the data is written, the mapping relation between the addresses of the logical units and the addresses of the physical units is adjusted according to the wear of the physical units. Finally, the data is written into the physical segment according to the master table.

Abstract: A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table.

Abstract: The present invention discloses a flash memory system comprising: a cache memory, a cache memory interface, a host interface, a flash memory interface, and a microprocessor The cache memory interface contains an arbitrator for performing data bus bandwidth time sharing process to access the cache memory The host interface is used for receiving data from a host system, and storing the data into the cache memory to form ready data The flash memory interface reads the ready data from the cache memory and stores it into at least one flash memory The microprocessor is used for controlling the host interface and the flash memory interface to access the cache memory Hence, the present invention can achieve the purpose of enhancing the access efficiency and increasing the life of the flash memory

Abstract: A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks.

Abstract: A control method of a memory storage device for writing an updated data from a host to the memory storage device is provided. The memory storage device provides storage space which is divided into a plurality of physical blocks to access the updated data. The control method includes the following steps: first, determining whether the updated data is a hot data or not; finally, storing the less updated data which is not the hot data into the physical block which has the higher erase counts according to the result of above determination.

Abstract: A flash controller performs a data correction function while executing a copy back procedure for a flash memory, and the flash memory includes at least one memory unit and a page buffer. The flash controller contains: a transmission buffer, an error correction unit, a correction information register, and a microprocessor. The microprocessor reads out a data from, the page buffer and stores the data into the transmission buffer after producing a read instruction of page copy to the flash memory. The microprocessor controls the error correction unit to check and correct the data in the transmission buffer and calculate a check result. The microprocessor produces a different program command to record the corrected data into the memory unit according to the data error quantity of the check result. Thereby, the present invention can achieve the purpose of improving the flash controller in reliability and access efficiency.

Abstract: The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.

Abstract: A method for memory space management is disclosed. It uses a resident program loaded into an operation system or the controller of a storage device to monitor the storage space and the resource allocation of the file system of the storage device. The status of the logical address with an erased and invalid data mapped with a physical block is checked via a L2P mapping table. By using a data erase instruction, the controller modifies the L2P mapping table to cancel the link relation between the physical block and the logical address and erase the physical block to release the memory space. Finally, the check location is stored for a next check. The method for memory space management improves the access speed and the usage life of the storage device.

Abstract: A flash memory controller with automatic interface mode switching is applied to a flash memory apparatus with a plurality of flash memories and the controller contains: a memory interface, a microprocessor, and an interface mode controller. The microprocessor recognizes the supported interface mode of every flash memory connected with the memory interface in an initial setting process, and individually sets the corresponding interface mode setting value into the interface mode controller. Thus, when the flash memory apparatus is operating in a normal operation state, the interface mode controller can output the corresponding interface mode setting value according to the present enabled flash memory, and the memory interface can adjust and switch the interface mode according to the interface mode setting value outputted by the interface mode controller. Thereby, the present invention can achieve the purpose whereby the flash memory apparatus can speed up accessing and increase efficiency.

Abstract: A storage system with a data recovery function and its method reduce errors in a storage medium to a recoverable range of a general ECC function by repeating a testing and recovery procedure for one or more times to assure the accuracy of reading data and enhance the data reliability effectively. The data recovery procedure includes the steps of providing test data by a test data generator of the storage system, writing the test data into a memory block where error data is found, finding an error bit by reading the test data, reducing the error to a recoverable range of the ECC technique by the recovery procedure. If the error bit cannot be found or reduced to a recoverable range of the ECC technique within an upper limit of the number of tests, the memory block is marked as bad.

Abstract: The present invention discloses a control method of an adaptive hybrid density memory storage device suitable for locating a data to the storage device. The storage device includes a high density memory unit and a low density memory unit. The method is characterized in that the property of the data is determined by its length, and the data is written to the high density memory unit or the low density memory unit according to the property of the data and the relative wearing rate and the amount of data processed by the storage device.

Abstract: A solid state semiconductor storage device with temperature control function comprises a non-volatile memory unit, a temperature sensing element, and a control unit. The temperature sensing element is used for sensing the operation temperature of the solid state semiconductor storage device so as to provide a temperature sensing signal to the control unit. According to the temperature sensing signal, the control unit controls the operation mode of the solid state semiconductor storage device for achieving the function of temperature control.

Abstract: The present invention discloses a control method for a hybrid density memory storage device. The method arranges physical locations for a file system stored in the storage device. The storage device includes a high density storage space, a low density storage space and a hot list capable of recording a plurality of logical locations. The method includes the following steps: receiving a command; verifying whether the logical location of the command belongs to the logical locations recorded in the hot list; and according to the verification, assigning a physical location of the high density storage space or a physical location of the low density storage space as the physical location corresponding to the logical location of the command.

Abstract: The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible.

Abstract: The present invention discloses a hybrid density memory storage device configured to store data responsive to a host and a file system thereof. The hybrid density memory storage device includes a non-volatile memory, a hot data buffer and a control unit. The non-volatile memory includes a high density storage space and a low density storage space. The control unit is coupled between the host, the non-volatile memory, and the hot data buffer. The control unit has a hot list used for recording a plurality of logical locations of hot data, and the control unit is capable of accessing data in/out the hot data buffer in accordance with the hot list.

Abstract: A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storage device includes a supply voltage booster, a non-volatile memory storage unit and a controller. The supply voltage booster boosts the lower supply voltage provided by the host device up to the higher operating voltage of the non-volatile memory. The controller adjusts the interface signal to a proper interface signal level by cooperating with the supply voltage and the operating voltage so as to avoid the interface from damage owing to an over high signal level or avoid the non-volatile memory unit from not correctly receiving signal due to an over low signal level.

Abstract: Storage apparatus can support various memory units with different standards based on the method which drives the power control-and-switch circuit in the power management unit according to a control signal caused by the ID code of a memory unit to control the second booster for further increasing the level of the external voltage or control the second regulator for further regulating or decreasing the level of the external voltage.

Abstract: A micro memory card includes a first housing having a first thickness and a first width; a first device connector formed on an end of the first housing, the first device connector conforming to a first device connection standard and allowing access to memory of the micro memory card by a device compatible with the first device connection standard; a second housing having a second thickness and a second width, the second housing being integrally joined with the first housing; and a second device connector formed on an end of the second housing at an opposite end of the micro memory card from the first device connector, the second device connector conforming to a second device connection standard and allowing access to memory of the micro memory card by a device compatible with the second device connection standard.