Abstract: A ventilation structure of a core chamber of a turbofan engine having a large bypass ratio, said structure comprising: an outer bypass wall surface (1), a core chamber wall surface (4) and a core casing (7). An outer bypass flow channel (2) is formed between the outer bypass wall surface (1) and the core chamber wall surface (4). A core chamber (6) is formed between the core chamber wall surface (4) and the core casing (7). An air intake annular cavity (3) is provided in the core casing and is located at the upstream position. The air intake annular cavity (3) is used to put the outer bypass flow channel (2) and the core chamber (6) in communication. An exhaust grille (5) is further provided on the core chamber wall surface (4) and is located at a tail position.

Abstract: A ventilation structure of a core chamber of a turbofan engine having a large bypass ratio, said structure comprising: an outer bypass wall surface (1), a core chamber wall surface (4) and a core casing (7). An outer bypass flow channel (2) is formed between the outer bypass wall surface (1) and the core chamber wall surface (4). A core chamber (6) is formed between the core chamber wall surface (4) and the core casing (7). An air intake annular cavity (3) is provided in the core casing and is located at the upstream position. The air intake annular cavity (3) is used to put the outer bypass flow channel (2) and the core chamber (6) in communication. An exhaust grille (5) is further provided on the core chamber wall surface (4) and is located at a tail position.

Abstract: A process compression method for compressing a process that includes a jump instruction includes the following steps: dividing the process into multiple blocks according to a position of the jump instruction in the process and a destination of the jump instruction; storing a jump relationship between these blocks; performing instruction compression on these blocks; updating a jump address of the jump instruction according to the jump relationship; determining multiple groups according to the sizes of the blocks and the jump relationship; and determining whether the jump instruction is a jump instruction of a first type or a jump instruction of a second type according to the relationship between the jump instruction and the groups.

Abstract: A process compression method for compressing a process that includes a jump instruction includes the following steps: dividing the process into multiple blocks according to a position of the jump instruction in the process and a destination of the jump instruction; storing a jump relationship between these blocks; performing instruction compression on these blocks; updating a jump address of the jump instruction according to the jump relationship; determining multiple groups according to the sizes of the blocks and the jump relationship; and determining whether the jump instruction is a jump instruction of a first type or a jump instruction of a second type according to the relationship between the jump instruction and the groups.

Abstract: The present disclosure relates to a protection circuit for a display device, a display device thereof, and a method for protecting a display device using a protection circuit. The display device includes a gate driving circuit, a level shift circuit, and a power management circuit. The level shift circuit is configured to provide an input signal to a signal input terminal of the gate driving circuit. The power management circuit is configured to provide power to the gate driving circuit. The protection circuit is configured to provide a power control signal to the power management circuit based on a current at the signal input terminal of the gate driving circuit, so that the power management circuit stops providing the power to the gate driving circuit.

Abstract: A display driving circuit is provided. The display driving circuit includes a source driver, a temperature detecting circuit, and a timing control circuit, wherein the temperature detecting circuit is connected to the timing control circuit, and is configured to detect a temperature of the source driver; and the timing control circuit is further connected to the source driver, and is configured to output a source signal to the source driver based on the temperature of the source driver; wherein a magnitude of a voltage of the source signal is negatively related to the temperature of the source driver.

Abstract: A direct memory access (DMA) circuit, its operation method, and a method of generating memory access commands are provided. The DMA circuit is used to access a memory according to a command and includes a register, a first channel controller, and a second channel controller. The operation method of the DMA circuit includes the following steps: decoding the command to obtain a first channel code and a second channel code, the first channel code corresponding to the first channel controller, and the second channel code corresponding to the second channel controller; obtaining a state of the first channel controller from the register according to the first channel code; selecting the second channel controller according to the second channel code; and controlling the second channel controller according to the state.

Abstract: A method for controlling a display panel includes: controlling polarities of data signals transmitted to pixel circuits in partial columns in a target display region to be inverted when a (KN?1)th frame is displayed; and controlling polarities of data signals transmitted to pixel circuits in other columns than the partial columns in the target display region to be inverted when a KNth frame is displayed.

Abstract: The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.

Abstract: The present disclosure relates to a protection circuit for a display device, a display device thereof, and a method for protecting a display device using a protection circuit. The display device includes a gate driving circuit, a level shift circuit, and a power management circuit. The level shift circuit is configured to provide an input signal to a signal input terminal of the gate driving circuit. The power management circuit is configured to provide power to the gate driving circuit. The protection circuit is configured to provide a power control signal to the power management circuit based on a current at the signal input terminal of the gate driving circuit, so that the power management circuit stops providing the power to the gate driving circuit.

Abstract: The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.

Abstract: A display driving circuit is provided. The display driving circuit includes a source driver, a temperature detecting circuit, and a timing control circuit, wherein the temperature detecting circuit is connected to the timing control circuit, and is configured to detect a temperature of the source driver; and the timing control circuit is further connected to the source driver, and is configured to output a source signal to the source driver based on the temperature of the source driver; wherein a magnitude of a voltage of the source signal is negatively related to the temperature of the source driver.

Abstract: A shift register unit and a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, connected to a pull-up node, and configured to charge the pull-up node according to an input signal; an output circuit, connected to the pull-up node and an output terminal, and configured to output an output signal to the output terminal under control of a voltage of the pull-up node; a reset circuit, connected to the pull-up node, and configured to reset the pull-up node; and a reset signal control circuit, connected to a first reset terminal and the reset circuit, and configured to generate and output a reset control signal according to a reset control input signal and a reset signal provided by the first reset terminal; the reset control signal is configured to control the reset circuit to perform a reset operation.

Abstract: A method for controlling a display panel includes: controlling polarities of data signals transmitted to pixel circuits in partial columns in a target display region to be inverted when a (KN?1)th frame is displayed; and controlling polarities of data signals transmitted to pixel circuits in other columns than the partial columns in the target display region to be inverted when a KNth frame is displayed.

Abstract: A shift register unit and a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, connected to a pull-up node, and configured to charge the pull-up node according to an input signal; an output circuit, connected to the pull-up node and an output terminal, and configured to output an output signal to the output terminal under control of a voltage of the pull-up node; a reset circuit, connected to the pull-up node, and configured to reset the pull-up node; and a reset signal control circuit, connected to a first reset terminal and the reset circuit respectively, and configured to generate and output a reset control signal according to a reset control input signal and a reset signal provided by the first reset terminal; and the reset control signal is configured to control the reset circuit to perform a reset operation.

Abstract: The present application discloses a display panel having a plurality of wirings in the fan-out area respectively connected to a plurality of signal lines in the display area, each of the plurality of wirings in the fan-out area configured to transmit a signal to one of a plurality of subpixels through one of the plurality of signal lines in the display area; and a plurality of bonding pads respectively connected to the plurality of wirings, configured to bond the plurality of wirings with a driver integrated circuit. The plurality of wirings are grouped into a plurality of groups of wirings comprising a first group of a plurality of first wirings and a second group of a plurality of second wirings. The plurality of first wirings are made of a first conductive material. The plurality of second wirings are made of a second conductive material. The second conductive material has a resistivity greater than that of the first conductive material.

Abstract: The present application discloses a display panel having a plurality of wirings in the fan-out area respectively connected to a plurality of signal lines in the display area, each of the plurality of wirings in the fan-out area configured to transmit a signal to one of a plurality of subpixels through one of the plurality of signal lines in the display area; and a plurality of bonding pads respectively connected to the plurality of wirings, configured to bond the plurality of wirings with a driver integrated circuit. The plurality of wirings are grouped into a plurality of groups of wirings comprising a first group of a plurality of first wirings and a second group of a plurality of second wirings. The plurality of first wirings are made of a first conductive material. The plurality of second wirings are made of a second conductive material. The second conductive material has a resistivity greater than that of the first conductive material.

Abstract: A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.