Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection circuit including a dynamic field plate bias circuit, and associated methods. In some embodiments, the ESD protection circuit includes a bipolar junction transistor (BJT) based ESD protection circuit including a field plate configured to increase a breakdown voltage of the BJT based ESD protection circuit. The ESD protection circuit also includes a dynamic field plate bias circuit coupled to the field plate of the BJT based ESD protection circuit. The dynamic field plate bias circuit is configured to provide the field plate a field plate bias at transient opposite to a field plate bias at a normal operation. The transient bias reduces a trigger voltage of the BJT based ESD protection circuit and increases a shunt current of the BJT based ESD protection circuit during the ESD event. Thereby, ESD protection reliability is improved.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a substrate, a first doping region, a second doping region, a third doping region, a first transient block unit and a second transient block unit. The first doping region is in the substrate. The second doping region is in the first doping region. The third doping region is in the first doping region. The first transient block unit is electrically connected to the second doping region. The second transient block unit is electrically connected between the third doping region and the first transient block unit.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection circuit including a dynamic field plate bias circuit, and associated methods. In some embodiments, the ESD protection circuit includes a bipolar junction transistor (BJT) based ESD protection circuit including a field plate configured to increase a breakdown voltage of the BJT based ESD protection circuit. The ESD protection circuit also includes a dynamic field plate bias circuit coupled to the field plate of the BJT based ESD protection circuit. The dynamic field plate bias circuit is configured to provide the field plate a field plate bias at transient opposite to a field plate bias at a normal operation. The transient bias reduces a trigger voltage of the BJT based ESD protection circuit and increases a shunt current of the BJT based ESD protection circuit during the ESD event. Thereby, ESD protection reliability is improved.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a substrate, a first doping region, a second doping region, a third doping region, a first transient block unit and a second transient block unit. The first doping region is in the substrate. The second doping region is in the first doping region. The third doping region is in the first doping region. The first transient block unit is electrically connected to the second doping region. The second transient block unit is electrically connected between the third doping region and the first transient block unit.

Abstract: An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.

Abstract: An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode.

Abstract: An integrated circuit device includes: a first chip including a first substrate and a main circuit formed on said first chip; a second chip stacked on the first substrate and including a second substrate that is independent from the first substrate, and a protective circuit for protecting the main circuit; and a conductive channel unit extending from the protective circuit and electrically connected to the main circuit.

Abstract: An electrostatic discharge (ESD) protection device includes a first transistor and a second transistor. The first transistor includes a first bulk electrode, a first electrode and a second electrode. The first bulk electrode and the first electrode form a first parasitic diode. The first bulk electrode and the second electrode form a second parasitic diode. The second transistor includes a second bulk electrode, a third electrode and a fourth electrode. The second bulk electrode and the third electrode form a third parasitic diode. The second bulk electrode and the fourth electrode form a fourth parasitic diode. The first bulk electrode is connected to the third electrode, and the second bulk electrode is connected to the first electrode.

Abstract: An electrostatic discharge (ESD) protection structure for a 3D IC is provided. The ESD protection structure includes a first active layer, a through-silicon via (TSV) device and a second active layer. The TSV is disposed in the first active layer, and the second active layer is stacked with the first active layer. The second active layer includes a substrate and an ESD protection device, wherein the ESD protection device having a doping area embedded in the substrate, and the ESD protection device electrically connects the TSV device.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first rail, a second rail, a first transistor and a resistance unit. The drain of the first transistor is electrically coupled to the first rail, and the source and gate of the first transistor are electrically coupled to the second rail. The resistance unit is electrically coupled between a body of the first transistor and the second rail. When ESD occurs, the resistance unit provides a resistance between the body of the first transistor and the second rail. An ESD protection device is also provided.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first rail, a second rail, a first transistor and a resistance unit. The drain of the first transistor is electrically coupled to the first rail, and the source and gate of the first transistor are electrically coupled to the second rail. The resistance unit is electrically coupled between a body of the first transistor and the second rail. When ESD occurs, the resistance unit provides a resistance between the body of the first transistor and the second rail. An ESD protection device is also provided.