Patents by Inventor Ming Feng Hsu

Ming Feng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10680620
    Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 9, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Yen-Yin Huang, Jung-Yu Chang, Ming-Feng Hsu
  • Publication number: 20190334529
    Abstract: A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 31, 2019
    Inventors: Yen-Yin HUANG, Jung-Yu CHANG, Ming-Feng HSU
  • Patent number: 10044536
    Abstract: Methods and apparatus are disclosed for data packetizing in an orthogonal frequency division multiplexing (OFDM) system. In order to improve transmission efficiency, the present invention uses independent packet and OFDDM block boundaries. Therefore, a packet is allowed to go across the OFDM block boundary and packed into two OFDM blocks. To indicate the start of each packet, a Frame Delimiter (FD) with a predefined format is inserted in front of each packet. The predefined format of the FD can be a predefined bit pattern or modulation points of modulation constellation. Idle data can also be inserted into OFDM blocks when no packet is ready. When data of one or more packets and idle data contain the predefined bit pattern of the FD, the data are modified to avoid generating the pre-defined bit pattern.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: August 7, 2018
    Assignee: Lilee Systems, LTD
    Inventors: Ming Feng Hsu, Ying Chuan Chen, Chia Chan Chang
  • Publication number: 20170222844
    Abstract: Methods and apparatus are disclosed for data packetizing in an orthogonal frequency division multiplexing (OFDM) system. In order to improve transmission efficiency, the present invention uses independent packet and OFDDM block boundaries. Therefore, a packet is allowed to go across the OFDM block boundary and packed into two OFDM blocks. To indicate the start of each packet, a Frame Delimiter (FD) with a predefined format is inserted in front of each packet. The predefined format of the FD can be a predefined bit pattern or modulation points of modulation constellation. Idle data can also be inserted into OFDM blocks when no packet is ready. When data of one or more packets and idle data contain the predefined bit pattern of the FD, the data are modified to avoid generating the pre-defined bit pattern.
    Type: Application
    Filed: January 26, 2017
    Publication date: August 3, 2017
    Inventors: Ming Feng Hsu, Ying Chuan Chen, Chia Chan Chang
  • Patent number: 9207083
    Abstract: In a navigation method for tracking a second electronic device using a first electronic device, the first electronic device receives position information of the second electronic device. A position of the second electronic device is marked on a navigation map stored in the first electronic device. The first electronic device is directed to track the second electronic device according to the marked position on the navigation map.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: December 8, 2015
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Ming-Feng Hsu
  • Patent number: 8983091
    Abstract: The disclosure provides a network signal receiving system and a network signal receiving method. The network signal receiving system comprises: a high pass filter, a canceller, and an adder. The high pass filter is utilized for performing a high pass filtering operation for an audio data signal to output at least a signal corresponding to transitions of the audio data signal, wherein the audio data signal is synchronized with a network data signal. The canceller is coupled to the high pass filter, and utilized for generating a noise cancelling signal according to the at least a signal output by the high pass filter. The adder is coupled to the canceller, utilized for receiving the network data signal and the noise cancelling signal, so as to use the noise cancelling signal to cancel at least a noise in the network data signal, which is corresponding to the at least a signal.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Hsuan-Ting Ho, Ming-Feng Hsu
  • Patent number: 8938771
    Abstract: A network receiver includes a first variable resistor, a second variable resistor, a first processing unit, a second processing unit and an adjusting circuit. The first variable resistor is coupled to a first transmission line via a first terminal for transmitting a first signal. The second variable resistor is coupled to a second transmission line via a second terminal for transmitting a second signal. The first processing unit is utilized for obtaining a difference according to the first signal and the second signal, and processing the difference to generate first data. The second processing unit is utilized for obtaining a summation according to the first signal and the second signal, and processing the summation to generate second data. The adjusting circuit is utilized for adjusting resistance(s) of at least one of the first variable resistor and the second variable resistor according to the first data and the second data.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: January 20, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Ching-Yao Su, Ming-Feng Hsu
  • Patent number: 8861573
    Abstract: A transceiver for dynamically adjusting a transmission clock includes: a transmitting unit, a receiving unit, and a transmission clock tracking unit. The transmitting unit is arranged for transmitting a transmission signal according to the transmission clock. The receiving unit is arranged for receiving a reception signal. The transmission clock tracking unit is coupled to the transmitting unit and the receiving unit, and arranged for dynamically controlling the transmission clock of the transmitting unit according to a reception clock corresponding to the reception signal.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 14, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Ching-Yao Su, Ming-Feng Hsu
  • Patent number: 8855111
    Abstract: A communication device has a transmitting circuit, a receiving circuit, and a controller. The transmitting circuit transmits a first data to a transmission line. The first data is generated by a first scrambler wherein the values of the registers of the first scrambler are characterized by a first combination number. The receiving circuit receives a second data scrambled by a second scrambler from the transmission line. The first and the second scramblers have the same scrambler generator polynomial. The receiving circuit has a descrambler having a plurality of registers for descrambling the second data. The values of the registers of the second scrambler are characterized by a second combination number when the descrambler descrambles the second data. The controller configures the values of the registers of the first scrambler according to the first combination number, the second combination number, and/or a difference between the first and the second combination numbers.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: October 7, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Ta-Chin Tseng, Ming-Feng Hsu, Yuan-Jih Chu
  • Patent number: 8848586
    Abstract: An electronic device with network connection functionality includes a transceiver chip and a processing circuit. The transceiver chip is utilized for processing a data corresponding to a physical (PHY) layer. The processing circuit is externally connected to the transceiver chip, for processing a data corresponding to a media access control (MAC) layer. When the transceiver chip receives a designated packet, the transceiver chip generates a notification signal to notify at least one portion of the processing circuit to be switched from a first operating mode to a second operating mode.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 30, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chun-Hung Liu, Liang-Wei Huang, Ming-Feng Hsu, Hsiao-Ming Huang
  • Patent number: 8804854
    Abstract: A network receiver and the adjusting method thereof, the network receiver includes a first delay unit, a second delay unit, a first processing unit and an adjusting circuit. The first delay unit is for delaying a first signal received from a first transmission line to generate a delayed first signal. The second delay unit is for delaying a second signal received from a second transmission line to generate a delayed second signal. The first processing unit is for processing a difference between the delayed first signal and the delayed second signal to generate first data. The adjusting circuit adjusts the first and second delay units to have a plurality of delay amount combinations, the first processing unit generates a plurality of first data respectively corresponding to the delay amount combinations, and the adjusting circuit adjusts delay amount of the first and second delay units according to the first data.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Hsuan-Ting Ho, Ming-Feng Hsu
  • Patent number: 8787844
    Abstract: A signal transceiving method, applied to a signal transceiver, includes: adjusting to approximate a value of a clock frequency of a signal to be transmitted from the signal transceiver to a value of a clock frequency of a received signal; performing an echo cancellation operation; computing a distance between a first certification code transmitted by the signal transceiver and a second certification code received by the signal transceiver; and stopping the echo cancellation operation when the distance is smaller than a threshold value.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: July 22, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Ching-Yao Su, Ming-Feng Hsu
  • Patent number: 8788858
    Abstract: A network device, for supporting a power saving mechanism through an auto-negotiation of HDMI, includes a transmitting circuit and a receiving circuit. The transmitting circuit is arranged for generating a link pulse signal to a second network device, wherein the network device and the second network device perform the auto-negotiation of a network connection by using the link pulse signal through HDMI in order to support the power saving mechanism. After the receiving circuit of the network device receives another link pulse signal transmitted from the second network device through HDMI, the network device is controlled to be operated under the power saving mechanism.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 22, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Liang-Wei Huang, Shieh-Hsing Kuo, Ming-Feng Hsu, Yuan-Jih Chu
  • Patent number: 8724680
    Abstract: A transceiver includes a transceiver and a clock generation unit. The clock generation unit includes a clock generator, a multiplexer, and a frequency difference detector. The transceiver exchanges data with a link partner according to a first clock generated by a phase-locked loop. The clock generator is used for generating and outputting a second clock. The multiplexer is used for receiving a calibration clock or a receiver clock of the link partner, and outputting the calibration clock or the receiver clock of the link partner. The frequency difference detector is used for generating a difference signal according to a difference between the calibration clock and the second clock, or a difference between the receiver clock of the link partner and the second clock. The clock generator adjusts the shift of the second clock according to the difference signal. The phase-locked loop generates the first clock according to the second clock.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 13, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ming-Feng Hsu, Kai-Yin Liu, Tzu-Han Hsu, Yuan-Jih Chu
  • Publication number: 20140067255
    Abstract: In a navigation method for tracking a second electronic device using a first electronic device, the first electronic device receives position information of the second electronic device. A position of the second electronic device is marked on a navigation map stored in the first electronic device. The first electronic device is directed to track the second electronic device according to the marked position on the navigation map.
    Type: Application
    Filed: August 1, 2013
    Publication date: March 6, 2014
    Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.
    Inventor: MING-FENG HSU
  • Patent number: 8572200
    Abstract: A master/slave decision device applied to a first network device is provided, where the first network device is coupled to a second network device, and the master/slave decision device includes a seed distance detection unit and a decision unit. The seed distance decision unit is utilized for detecting a seed distance between a first seed utilized in a first scrambler of the first network device and a second seed utilized in a second scrambler of the second network device. The decision unit is coupled to the seed distance detecting unit, and is utilized for determining the first network device to be a master device or a slave device according to the seed distance.
    Type: Grant
    Filed: July 3, 2011
    Date of Patent: October 29, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chi-Shun Weng, Liang-Wei Huang, Ming-Feng Hsu, Yuan-Jih Chu
  • Publication number: 20130128933
    Abstract: A transceiver includes a transceiver and a clock generation unit. The clock generation unit includes a clock generator, a multiplexer, and a frequency difference detector. The transceiver exchanges data with a link partner according to a first clock generated by a phase-locked loop. The clock generator is used for generating and outputting a second clock. The multiplexer is used for receiving a calibration clock or a receiver clock of the link partner, and outputting the calibration clock or the receiver clock of the link partner. The frequency difference detector is used for generating a difference signal according to a difference between the calibration clock and the second clock, or a difference between the receiver clock of the link partner and the second clock. The clock generator adjusts the shift of the second clock according to the difference signal. The phase-locked loop generates the first clock according to the second clock.
    Type: Application
    Filed: September 11, 2012
    Publication date: May 23, 2013
    Inventors: Ming-Feng Hsu, Kai-Yin Liu, Tzu-Han Hsu, Yuan-Jih Chu
  • Publication number: 20130100990
    Abstract: A transceiver for dynamically adjusting a transmission clock includes: a transmitting unit, a receiving unit, and a transmission clock tracking unit. The transmitting unit is arranged for transmitting a transmission signal according to the transmission clock. The receiving unit is arranged for receiving a reception signal. The transmission clock tracking unit is coupled to the transmitting unit and the receiving unit, and arranged for dynamically controlling the transmission clock of the transmitting unit according to a reception clock corresponding to the reception signal.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 25, 2013
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Ching-Yao Su, Ming-Feng Hsu
  • Publication number: 20130072133
    Abstract: A signal transceiving method, applied to a signal transceiver, includes: adjusting to approximate a value of a clock frequency of a signal to be transmitted from the signal transceiver to a value of a clock frequency of a received signal; performing an echo cancellation operation; computing a distance between a first certification code transmitted by the signal transceiver and a second certification code received by the signal transceiver; and stopping the echo cancellation operation when the distance is smaller than a threshold value.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 21, 2013
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Ching-Yao Su, Ming-Feng Hsu
  • Publication number: 20130051578
    Abstract: The disclosure provides a network signal receiving system and a network signal receiving method. The network signal receiving system comprises: a high pass filter, a canceller, and an adder. The high pass filter is utilized for performing a high pass filtering operation for an audio data signal to output at least a signal corresponding to transitions of the audio data signal, wherein the audio data signal is synchronized with a network data signal. The canceller is coupled to the high pass filter, and utilized for generating a noise cancelling signal according to the at least a signal output by the high pass filter. The adder is coupled to the canceller, utilized for receiving the network data signal and the noise cancelling signal, so as to use the noise cancelling signal to cancel at least a noise in the network data signal, which is corresponding to the at least a signal.
    Type: Application
    Filed: August 30, 2012
    Publication date: February 28, 2013
    Inventors: Yuan-Jih Chu, Liang-Wei Huang, Hsuan-Ting Ho, Ming-Feng Hsu