Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.

Abstract: A mold set for manufacturing a case is provided. The mold set comprises an upper mold having a fluid channel; a lower mold facing the upper mold; and a drawing mold disposed between the upper mold and the lower mold, wherein the mold set has a case forming space formed among the upper mold, the lower mold and the drawing mold, and the mold set has a sharp-edge forming space communicating with the case forming space, and formed between the drawing mold and the lower mold.

Abstract: A mold set for manufacturing a case is provided. The mold set comprises an upper mold having a fluid channel; a lower mold facing the upper mold; and a drawing mold disposed between the upper mold and the lower mold, wherein the mold set has a case forming space formed among the upper mold, the lower mold and the drawing mold, and the mold set has a sharp-edge forming space communicating with the case forming space, and formed between the drawing mold and the lower mold.

Abstract: An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi2-x) for the source and drain is described. The structure includes a suitable capping layer stack.

Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

Abstract: This invention relates to a semiconductor device making use of a highly thermal robust metal electrode as gate material. In particular, the development of Hafnium Nitride as a metal gate electrode (or a part of the metal gate stack) is taught and its manufacturing steps of fabrication with different embodiments are shown.

Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

Abstract: A gate electrode for semiconductor devices, the gate electrode comprising a mixture of a metal having a work function of about 4 eV or less and a metal nitride.

Abstract: An electromagnetic forming device for a sheet of material is provided. The electromagnetic forming device includes a fixing base, a magnetic concentration block, an electromagnetic actuator, and a die. The fixing base has a groove. The magnetic concentration block is disposed in the groove of the fixing base, and has an accommodating space therein, which is in communication with a surface of the magnetic concentration block via a slit. The electromagnetic actuator, used to generate a magnetic field, is disposed in the accommodating space of the magnetic concentration block, but does not contact the magnetic concentration block. The die and the magnetic concentration block are separated by a gap, and a sheet of material can be disposed in the gap. As the magnetic concentration block is a block, eddy currents in the magnetic concentration block are distributed uniformly, so the generated magnetic field is also distributed uniformly, thus exerting a uniform forming force on the sheet of material.

Abstract: A double barrier resonant tunneling diode (RTD) is formed and integrated with a level of CMOS/BJT/SiGe devices and circuits through processes such as metal-to-metal thermocompressional bonding, anodic bonding, eutectic bonding, plasma bonding, silicon-to-silicon bonding, silicon dioxide bonding, silicon nitride bonding and polymer bonding or plasma bonding. The electrical connections are made using conducting interconnects aligned during the bonding process. The resulting circuitry has a three-dimensional architecture. The tunneling barrier layers of the RTD are formed of high-K dielectric materials such as SiO2, Si3N4, Al2O3, Y2O3, Ta2O5, TiO2, HfO2, Pr2O3, ZrO2, or their alloys and laminates, having higher band-gaps than the material forming the quantum well, which includes Si, Ge or SiGe. The inherently fast operational speed of the RTD, combined with the 3-D integrated architecture that reduces interconnect delays, will produce ultra-fast circuits with low noise characteristics.

Abstract: A gate electrode for semiconductor devices, the gate electrode comprising a mixture of a metal having a work function of about 4 eV or less and a metal nitride.

Abstract: This invention relates to a semiconductor device making use of a highly thermal robust metal electrode as gate material. In particular, the development of Hafnium Nitride as a metal gate electrode (or a part of the metal gate stack) is taught and its manufacturing steps of fabrication with different embodiments are shown.

Abstract: Briefly, a preferred embodiment of the present invention includes a metal-insulator-metal (MIM) capacitor including a bottom layer of conductive material formed by depositing this conductive material on a substrate. A dielectric material is then formed on the bottom conductive layer, wherein the dielectric material is preferably an HfO2 dielectric doped with lanthamide material, more preferably Th doped HfO2 with a Th concentration in the range of 0 to 6% and more particularly substantially 4%. A top conductive layer is formed on top of the dielectric.