Abstract: A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A digital switch includes a switching fabric that switches data between a plurality of ports. The switching fabric includes data lines and a control line. An arbitrator arbitrates traffic between the plurality of ports. A command processor receives a command over the control line and modifies a switching fabric parameter in response to the command. The control line is preferably the same line that is not used during normal switching fabric operation, such as, for example, an ABORT line, or ABORT pin.

Abstract: A network switch includes a plurality of cross points each having a plurality of ports, a switching fabric that routes traffic between the plurality of cross points, and an arbitrator that arbitrates the traffic in a cut-through mode for packets larger than a predetermined size, and in a store and forward mode for packets smaller than the predetermined size.

Abstract: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

Abstract: A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached.

Abstract: An IPC/IGC Bus Translator (IBT) translates between data formats including packets and narrow cells. IBT processes received packets, parsing them into cells or one or more cell formats. The invention is a system and method that selects the appropriate cell format based on predetermined factors. In one embodiment, the topology and configuration of the IPC/IGC components are factors used to determine the appropriate cell format. In another embodiment, the IBT receives cells and processes the received cells into packets. In one embodiment, the IBT translates packets receives in a parallel architecture into cells in a serial architecture. The translator operates with packets in a parallel configuration and narrow cells in a serial configuration. A narrow cell format has a header and payload. The header includes a special character and control information. The payload includes data.

Abstract: The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Abstract: A switching fabric having cross points that process multiple stripes of serial data. Each cross point includes a plurality of port slices and ports. Each port includes a plurality of FIFOs, a FIFO read arbitrator, a multiplexer, a dispatcher, and an accumulator. In one embodiment, each cross point has eight ports and eight port slices. A method for processing a stripe of data at a cross point at one port slice includes storing data received from other port slices in a plurality of FIFOs and arbitrating the reading of the stored data. A step of writing data received from a port at the one port slice to an appropriate FIFO in a different port slice is also included. In one embodiment, a method for processing data in port slice based on wide cell encoding and an external flow control command is provided.

Abstract: A CMOS 4-2 carry-save adder cell implementation. A XNOR gate is used in the computation of SUM and CARRY. By using an XNOR gate, there are no possible input permutations which will cause any output in the SUM logic to be driven by two P-channel devices in series. The final XOR function needed to compute the SUM output is performed by a 2-to-1 multiplexor and two inverters. The maximum resistance from input to output of the 2-to-1 multiplexor is relatively low, and the worst case is when the CIN input drives through the transmission gate. The input capacitances are very low. The maximum load driven by the output is low because the output never drives through the drains of any transistors. Instead, the output drives only the gates of four transistors to implement the XOR function. A single 8-transistor complex gate and an inverter are used to calculate COUT. The transistors in the complex gate can be made relatively small, thus minimizing the input capacitance.