Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Abstract: The present disclosure discloses a method and system for identifying a foreign object on a transmission line, a computer device, and a medium, and relates to the field of image identification technologies. According to the present disclosure, an impact of an environment on a transmission line inspection image is eliminated by using the super-resolution reconstruction defogging algorithm, then the transmission line image is semantically segmented by using an image segmentation algorithm to reduce an impact of a background image on identification of the foreign object on the transmission line, and finally, the foreign object on the transmission line is quickly and accurately identified according to the transmission line foreign object sample database constructed based on a segment anything model and an object morphological augmentation algorithm.

Abstract: A wafer-scale system-in-package structure and a forming method thereof are disclosed. The package structure includes: a substrate, where the substrate includes an upper surface and a lower surface that are opposite to each other; a first molding layer that wraps the plurality of semiconductor chips and the upper surface of the substrate; external protrusions on the lower surface of the substrate; and a second molding layer that wraps side surfaces of the plurality of external protrusions and the lower surface of the substrate, where a thickness of the second molding layer is less than a thickness of the first molding layer, and at least one of the coefficient of thermal expansion or Young's modulus of the second molding layer is equal to or higher than that of the first molding layer. In this way, warpage of the system-in-package structure can be effectively controlled.

Abstract: Disclosed herein are methods, devices and systems including a substrate, a transistor channel on the substrate and extending in direction parallel to the substrate, a first electrode extending in a direction orthogonal to the substrate and coupled to the transistor channel, a second electrode coupled to the transistor channel and extending in a direction orthogonal to the substrate and parallel to the first electrode, and a first epitaxial structure arranged between the transistor channel and the first electrode. The first epitaxial structure may share a common crystalline orientation with the transistor channel, and may separate a surface of the first electrode and a surface of the transistor channel in a direction parallel to the substrate by a distance varying along the length of the first electrode.

Abstract: A method, apparatus, and system are provided. The method includes the steps of depositing a dummy stressor into a source and drain (S/D) region between a first sidewall and a second sidewall of a transistor before an epitaxial (EPI) layer is deposited into the S/D region; removing a polysilicon fin between the second sidewall and a third sidewall of the transistor to expose an initial stack; removing the dummy stressor from the S/D region; and depositing the EPI layer into the S/D region.

Abstract: The present disclosure discloses a method and a system for evaluating an operating state of electric energy data acquisition equipment, and a medium, and relates to the field of equipment state evaluation technologies. Firstly, regulation information of the electric energy data acquisition equipment is analyzed, and an operating state evaluation baseline of the electric energy data acquisition equipment is obtained. Operating profile data of the electric energy data acquisition equipment is acquired, and an operating state evaluation rule is established based on the operating profile data and the operating state evaluation baseline. Finally, operating state evaluation is performed on the electric energy data acquisition equipment based on the operating state evaluation rule, to obtain an operating state evaluation result.

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Abstract: This application provides a route display method performed by a computer device. When a route planning request for a route planning mode is obtained from a terminal device, a corresponding route planning result and original interpretation data involved in the current route planning result are determined; a route interpretation scenario corresponding to the original interpretation data and the route planning mode are used to query a corresponding target interpretation template; and a target interpretation element that needs to be displayed when the route planning result is displayed in an electronic map on the terminal device is determined through the target interpretation template, to explain the route planning result by using the target interpretation element. Such a manner of interpreting templates can store, query, modify and synchronize the interpretation templates through a database, so that combinations of various route planning modes and route interpretation scenarios can be decoupled from each other.

Abstract: A high-voltage box and an energy storage system are provided. The high-voltage box includes a main body, a battery management system, and an electrical module. The battery management system and the electrical module are detachably installed in the main body. The battery management system and the electrical module are provided adjacent to each other and are connected. The electrical module includes a substrate and a plurality of electrical components. The substrate is provided with a plurality of installation regions for installing the electrical components. The substrate is further provided with an adapter with a plurality of interfaces for connection with the electrical components and an external battery system respectively.

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

Abstract: Provided are systems, methods, and apparatuses for applying stress in transistors. In one or more examples, the systems, devices, and methods include depositing an epitaxial film on a surface between a first sidewall and a second sidewall of the transistor; depositing a dielectric over the epitaxial film and on the surface between the first sidewall and the second sidewall to increase stress in a silicon channel of the transistor; removing a polysilicon fin between the second sidewall and a third sidewall; and depositing a first metal between the second sidewall and the third sidewall based on removing the polysilicon fin.

Abstract: According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.

Abstract: A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

Abstract: A modular lifting apparatus includes a vehicle body assembly and a drive control assembly. The vehicle body assembly includes a vehicle body and a pedal component, and the pedal component is connected to the vehicle body. The drive control assembly is disposed on the vehicle body, and includes a control component, a drive component and an auxiliary guide component. The control component is connected to the drive component. The drive component and the auxiliary guide component are used to cooperate with a guide body to allow the vehicle body to move in an extension direction of the guide body.

Abstract: A method for manufacturing a semiconductor device according to one or more embodiments may include growing a first epitaxy layer at a first side and a second side of a stack of gates and channels, applying a sacrificial layer on the first epitaxy layer, growing a second epitaxy layer on the sacrificial layer, removing the sacrificial layer, and depositing a metal layer on the first epitaxy layer and the second epitaxy layer at the first side of the stack of gates and channels.

Abstract: The invention discloses a 4-(N-methyl) aminopiperidine myricetin derivatives containing sulfonamide, a preparation method and application, whose structural general formula is shown as follows: Wherein, R is substituted phenyl and substituted aromatic heterocyclic group; n is the number of carbon in the carbon chain and is 2, 3, 4 and 5 respectively. The substituted phenyl group is an alkyl group containing C1-6, an alkoxy group containing C1-6, a nitro group, a halogen atom or a hydrogen atom in ortho, meta and para positions on the benzene ring. The substituted aromatic heterocyclic group is thienyl, furyl, pyrrolyl, pyridyl, etc., and the substituent on the aromatic heterocyclic ring is an alkyl group containing C1-6, alkoxy group of C1-6, nitro group, halogen atom or hydrogen atom in ortho, meta and para positions. The invention has a better control effect on inhibiting plant germs and can be used as an agricultural bactericide.

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).