Abstract: A judging method for a module peeling time of a soft electronic fabric module is provided. The method includes: preselecting a plurality of module material combinations, the plurality of module material combinations respectively comprising a substrate material, a wire material and a packaging material; extracting the plurality of module material combinations to generate a plurality of module material combination parameters; generating a plurality of machine learning training data based on the plurality of module material combination parameters and a plurality of module pre-processing conditions; and training a machine learning model according to the plurality of machine learning training data to provide an optimized prediction model for judging a module peeling time.

Abstract: Various aspects of the present disclosure relate to a method of cleaning a glass substrate. The method includes contacting the glass substrate with a cleaning agent for a predetermined amount of time. The cleaning agent includes a substance having a sublimation point in a range of from about ?90° C. to about ?70° C. and the cleaning agent is dispersed in a gas carrier.

Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

Abstract: An adaptive vehicle headlight is provided for being installed on a vehicle body for use. The adaptive vehicle headlight includes a light body, an optical lens, a driver, and a control unit. The optical lens, the driver, and the control unit are integrated into the light body. In practice, the optical lens can optionally include a light distributing member. The control unit can cause an operation of the driver according to a tilt angle of the vehicle body, such that the optical lens and/or the light distributing member are rotated to a predetermined angle, so as to produce an illumination pattern in a horizontal state.

Abstract: An underwater sonar device and an underwater detecting system. The underwater sonar device comprises a main body, a propeller, a detector and a hydrofoil assembly. The main body is an axisymmetric structure. The propeller, the detector, and the hydrofoil assembly are disposed on the main body. The detector is configured to detect and image an underwater target. The propeller is configured to drive the main body to move along a longitudinal direction and a vertical direction, and control a pitch angle, a roll angle, and a yaw angle of the main body. The hydrofoil assembly is disposed at a back of the main body, and is configured to adjust an included angle between the hydrofoil assembly and the longitudinal direction of the main body automatically based on water resistance on the hydrofoil assembly to keep the sonar device navigating at a fixed depth.

Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.

Abstract: A triboelectric nanogenerating device is configured for providing an electric power to an electronic device and the triboelectric nanogenerating device includes at least one scaly triboelectric membrane configured for providing the electric power to the electronic device by frictional electrification. The at least one scaly triboelectric membrane includes a keratin and a polyvinyl alcohol, the at least one scaly triboelectric membrane has a first triboelectric surface, and the first triboelectric surface of the at least one scaly triboelectric membrane includes a plurality of scaly layers. Each of the scaly layers is arranged in order and extends along an orienting direction. A distal end of each of the scaly layers has a plurality of saw-tooth structures.

Abstract: Provided in the present application are a paging processing method and apparatus, and a storage medium. The paging processing method is applied to a multi-card terminal device, and the method includes: in response to that a second subscriber identity card in an idle state in the multi-card terminal device receives a paging message sent from a second network device, sending, by a first subscriber identity card in a connected state in the multi-card terminal device, first busy indication information to a first core network device. The first busy indication information is used to indicate that the multi-card terminal device has received the paging message of the second network device and decided not to respond temporarily.

Abstract: A method of acquiring feature information of a detected object is provided, including: controlling the detected object to pass through a detection apparatus; controlling an imaging system to perform radiation scanning on the detected object acquiring a radiation scanning image of the detected object acquiring feature information of the detected object through the radiation scanning image. The detected object includes a first part, a detection part and a second part sequentially in a first direction. The acquiring feature information of the detected object through the radiation scanning image includes: acquiring a first boundary line between the detection part and the first part and a second boundary line between the detection part and the second part through the radiation scanning image; and calculating a dimension between the first boundary line and the second boundary line in the first direction to acquire a dimension of the detection part in the first direction.

Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

Abstract: Methods leverage premixed gas mixtures to perform a metrology process on a substrate using an inline secondary ion mass spectrometry (SIMS) process. The premixed gas mixture of two or more gases is injected into a plasma chamber that is configured to produce sputtering ions for the inline SIMS process. The two or more gases produce non-metallic ion species which are compatible with downstream substrate fabrication processes and allow further fabrication to be performed on the substrate after the inline SIMS process has completed. The sputtering ions are ejected from the plasma chamber into a magnetic field. The intensity of the magnetic field is altered to select a single species of ions. The single species of ions are directed towards a surface of the substrate and secondary ions sputtered from the surface of the substrate by the selected species of ions are detected and analyzed.

Abstract: The present disclosure provides novel pladienolide compounds, pharmaceutical compositions containing such compounds, and methods for using the compounds as therapeutic agents. These compounds may be useful in the treatment of cancers, particularly cancers in which agents that target the spliceosome and mutations therein are known to be useful. Also provided herein are methods of treating cancers by administering at least one compound disclosed herein and at least one additional therapy.

Abstract: An image enhancement method includes: acquiring an image in a YUV format (110); performing N max layers of wavelet decomposition on a brightness component and chrominance components respectively (120); starting from the (N max)th layer, performing wavelet reconstruction on the low frequency sub-bands of the chrominance components of each layer on which edge preserving filtering has been performed according to the low frequency sub-band of the brightness component of the corresponding layer, and the high frequency sub-bands of the chrominance components continuously towards an upper layer until an image of an original size is obtained (130); performing, according to the brightness component, edge preserving filtering on the chrominance components that have been subjected to the wavelet reconstruction (140); integrating the chrominance components that have been subjected to the edge preserving filtering and the brightness component (150).

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a gate electrode, and a protection layer. The doped nitride-based semiconductor layer has a first portion and a second portion over the first portion and narrower than the first portion. The gate electrode is disposed over the doped nitride-based semiconductor layer and narrower than the first portion. The protection layer is disposed over the doped nitride-based semiconductor layer and the gate electrode. A top surface of the first portion of the doped nitride-based semiconductor layer is covered by the protection layer, and a sidewall of the first portion of the doped nitride-based semiconductor layer is free from coverage by the protection layer.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Abstract: A memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a signal electrode and a counter electrode, the capacitor is over the transistor, and the signal electrode is electrically coupled to the second conductive region of the transistor and isolated from the first conductive region of the transistor. The counter electrode includes a plurality of sub-electrodes electrically connected with each other.

Abstract: A memory structure includes a semiconductor substrate, an active region, a transistor, and a buried-WL (word line). The semiconductor substrate has an original semiconductor surface. The active region is in the semiconductor substrate and surrounded by a shallow trench isolation (STI) region. The transistor is formed based on the active region. The buried-WL (word line) extends through the active region and the STI region. The buried-WL has variable depth or width along the extension direction of the buried-WL.

Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.

Abstract: A transistor structure includes a semiconductor substrate, a gate region a spacer, a first trench, a first isolation region and a conductive region. The semiconductor substrate has an active region which has a semiconductor surface. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. The spacer covers a sidewall of the gate region. The first trench is formed below the semiconductor surface of the semiconductor substrate in the active region. The first isolation region is in the first trench. The conductive region is positioned on the first isolating region. Wherein a lateral length of the first conductive portion is greater than that of the second conductive portion.