Patents by Inventor Ming-Hong Hsieh
Ming-Hong Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047345Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: CHUN-WEI CHANG, HSUAN-MING HUANG, JIAN-HONG LIN, MING-HONG HSIEH, MINGNI CHANG, MING-YIH WANG
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Publication number: 20230386973Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Ming-Hong HSIEH, Ming-Yih WANG, Yinlung LU
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Patent number: 11830806Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: GrantFiled: April 29, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wei Chang, Hsuan-Ming Huang, Jian-Hong Lin, Ming-Hong Hsieh, Mingni Chang, Ming-Yih Wang
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Patent number: 11616002Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: GrantFiled: January 29, 2021Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu
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Publication number: 20230066291Abstract: A semiconductor arrangement includes a heat source above an interconnect layer and below a heat conductor. The heat conductor is coupled to a heat sink by a thermally conductive bonding layer. Heat from the heat source is conducted through the heat conductor in a direction opposite the direction of the interconnect layer, through the thermally conductive bonding layer, and to a heat sink. The heat conductor includes an arrangement of dielectric layers, dummy metal layers, and dummy VIA layers.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Chih-Wei Lin, Ming-Hsien Lin, Ming-Hong Hsieh, Jian-Hong Lin
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Publication number: 20220367323Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu
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Publication number: 20220352067Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: ApplicationFiled: April 29, 2021Publication date: November 3, 2022Inventors: CHUN-WEI CHANG, HSUAN-MING HUANG, JIAN-HONG LIN, MING-HONG HSIEH, MINGNI CHANG, MING-YIH WANG
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Publication number: 20210375723Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: January 29, 2021Publication date: December 2, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Ming-Hong HSIEH, Ming-Yih WANG, Yinlung LU
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Patent number: 9875964Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: GrantFiled: January 28, 2014Date of Patent: January 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Publication number: 20140145194Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: ApplicationFiled: January 28, 2014Publication date: May 29, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Patent number: 8648592Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: GrantFiled: September 13, 2011Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Publication number: 20130063175Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
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Patent number: 7436009Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.Type: GrantFiled: April 4, 2007Date of Patent: October 14, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chen Huang, Chien-Chung Fu, Ming-Hong Hsieh, Hui Ouyang, Yi-Nien Su, Hun-Jan Tao
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Publication number: 20070184669Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.Type: ApplicationFiled: April 4, 2007Publication date: August 9, 2007Inventors: Yi-Chen Huang, Chien Fu, Ming-Hong Hsieh, Hui Ouyang, Yi-Nien Su, Hun-Jan Tao
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Patent number: 7217663Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.Type: GrantFiled: January 18, 2005Date of Patent: May 15, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yi-Chen Huang, Chien Chung Fu, Ming-Hong Hsieh, Hui Ouyang, Yi-Nien Su, Hun-Jan Tao
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Publication number: 20060160362Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.Type: ApplicationFiled: January 18, 2005Publication date: July 20, 2006Inventors: Yi-Chen Huang, Chien Fu, Ming-Hong Hsieh, Hui Ouyang, Yi-Nien Su, Hun-Jan Tao
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Patent number: 6999081Abstract: A new data processing and display method for use in interactive manufacturing process management is achieved. A first variable value, such as WIP, for a manufacturing stage is uploaded from a database and is subtracted from a first target value to obtain a first variable variance. A first variable variance bar is displayed above a stage axis on a graphical display device and is non-filled if the first variable variance is positive and is filled if the first variable variance is negative. A second variable value, such as production moves, is uploaded and is subtracted from a second target value to obtain a second variable variance. A second variable value bar is displayed below the stage axis on the graphical display device and is non-filled. A second variable variance bar is displayed below the second variable value bar on the graphical display device if the second variable variance is positive.Type: GrantFiled: November 14, 2001Date of Patent: February 14, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo-Chen Lin, Ming-Hong Hsieh
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Patent number: 6974505Abstract: A cleaning tool for cleaning substrates, comprising a circulation conduit through which is circulated a cleaning liquid or gas. The circulation conduit is disposed in fluid communication with an upstream flow chamber and a downstream cleaning chamber, the cross-sectional area of which cleaning chamber is less than the cross-sectional area of the flow chamber. In use, the cleaning chamber receives a wafer substrate for cleaning of particles or removal of polymer films from the substrate. The smaller cross-sectional area of the cleaning chamber accelerates the flow of a cleaning fluid flowing through the cleaning chamber from the flow chamber. The rapidly-flowing cleaning fluid removes the particles and/or films from the substrate while preventing dropping of the removed particles or re-deposition of the film back onto the substrate. A particle filter may be provided in the circulation conduit downstream of the cleaning chamber for removing the particles.Type: GrantFiled: October 16, 2002Date of Patent: December 13, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ching Shih, Chun-Li Chou, Ming-Hong Hsieh, Hong-J. Tao
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Publication number: 20040074521Abstract: A cleaning tool for cleaning substrates, comprising a circulation conduit through which is circulated a cleaning liquid or gas. The circulation conduit is disposed in fluid communication with an upstream flow chamber and a downstream cleaning chamber, the cross-sectional area of which cleaning chamber is less than the cross-sectional area of the flow chamber. In use, the cleaning chamber receives a wafer substrate for cleaning of particles or removal of polymer films from the substrate. The smaller cross-sectional area of the cleaning chamber accelerates the flow of a cleaning fluid flowing through the cleaning chamber from the flow chamber. The rapidly-flowing cleaning fluid removes the particles and/or films from the substrate while preventing dropping of the removed particles or re-deposition of the film back onto the substrate. A particle filter may be provided in the circulation conduit downstream of the cleaning chamber for removing the particles.Type: ApplicationFiled: October 16, 2002Publication date: April 22, 2004Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Ching Shih, C.L. Chou, Ming-Hong Hsieh, Hun-Jan Tao