Patents by Inventor Ming-Hsien Tu
Ming-Hsien Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974367Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.Type: GrantFiled: October 4, 2022Date of Patent: April 30, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
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Patent number: 9466357Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.Type: GrantFiled: January 22, 2015Date of Patent: October 11, 2016Assignee: Faraday Technology Corp.Inventors: Ching-Te Chuang, Chien-Yu Lu, Ming-Ching Zheng, Ming-Hsien Tu
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Patent number: 9275726Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.Type: GrantFiled: March 7, 2014Date of Patent: March 1, 2016Assignee: Faraday Technology Corp.Inventors: Ching-Te Chuang, Chih-Hao Chang, Chao-Kuei Chung, Chien-Yu Lu, Shyh-Jye Jou, Ming-Hsien Tu
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Publication number: 20160027500Abstract: A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.Type: ApplicationFiled: January 22, 2015Publication date: January 28, 2016Inventors: Ching-Te Chuang, Chien-Yu Lu, Ming-Ching Zheng, Ming-Hsien Tu
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Patent number: 9159403Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.Type: GrantFiled: January 10, 2013Date of Patent: October 13, 2015Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Li-Wei Chu, Chi-Shin Chang, Ming-Hsien Tu
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Publication number: 20150162077Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.Type: ApplicationFiled: March 7, 2014Publication date: June 11, 2015Applicants: NATIONAL CHIAO TUNG UNIVERSITY, FARADAY TECHNOLOGY CORP.Inventors: Ching-Te Chuang, Chih-Hao Chang, Chao-Kuei Chung, Chien-Yu Lu, Shyh-Jye Jou, Ming-Hsien Tu
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Patent number: 8854897Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.Type: GrantFiled: November 1, 2012Date of Patent: October 7, 2014Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu
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Patent number: 8837207Abstract: A static memory and a static memory cell are provided. The static memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch, a second switch, a third switch, a first pull-down switch, and a second pull-down switch. When a data writing operation is performed, the latching capability of the latch circuit constituted by the first to the sixth transistors is disabled by turning off the second transistor or the fifth transistor, so that the speed of the data writing operation is increased and the data writing performance is improved. The first switch and the second switch provide a path for reading or writing data, and the third switch is coupled to a bit line for receiving data from or transmitting data to the bit line.Type: GrantFiled: October 9, 2013Date of Patent: September 16, 2014Assignee: National Chiao Tung UniversityInventors: Shyh-Jye Jou, Ming-Hsien Tu, Yu-Hao Hu, Ching-Te Chuang, Yi-Wei Chiu
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Patent number: 8804445Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Patent number: 8773894Abstract: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.Type: GrantFiled: November 26, 2012Date of Patent: July 8, 2014Assignee: National Chiao Tung UniversityInventors: Ching-Te Chuang, Hao-I Yang, Chien-Yu Lu, Chien-Hen Chen, Chi-Shin Chang, Po-Tsang Huang, Shu-Lin Lai, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu
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Patent number: 8693237Abstract: A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.Type: GrantFiled: July 31, 2012Date of Patent: April 8, 2014Assignee: National Chiao Tung UniversityInventors: Shyh-Jye Jou, Jhih-Yu Lin, Ching-Te Chuang, Ming-Hsien Tu, Yi-Wei Chiu
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Publication number: 20140078818Abstract: A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.Type: ApplicationFiled: November 26, 2012Publication date: March 20, 2014Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Ching-Te CHUANG, Hao-I YANG, Chien-Yu LU, Chien-Hen CHEN, Chi-Shin CHANG, Po-Tsang HUANG, Shu-Lin LAI, Wei HWANG, Shyh-Jye JOU, Ming-Hsien TU
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Publication number: 20140063918Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.Type: ApplicationFiled: January 10, 2013Publication date: March 6, 2014Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Ching-Te CHUANG, Nan-Chun LIEN, Wei-Nan LIAO, Li-Wei CHU, Chi-Shin CHANG, Ming-Hsien TU
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Publication number: 20140009999Abstract: A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.Type: ApplicationFiled: November 1, 2012Publication date: January 9, 2014Inventors: Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, Ming-Hsien Tu
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Publication number: 20130223136Abstract: The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.Type: ApplicationFiled: May 31, 2012Publication date: August 29, 2013Applicant: National Chiao Tung UniversityInventors: Ching-Te CHUANG, Shyh-Jye Jou, Wei Hwang, Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Publication number: 20130222071Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.Type: ApplicationFiled: May 31, 2012Publication date: August 29, 2013Applicant: National Chiao Tung UniversityInventors: Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
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Publication number: 20130194861Abstract: A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.Type: ApplicationFiled: July 31, 2012Publication date: August 1, 2013Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Shyh-Jye Jou, Jhih-Yu Lin, Ching-Te Chuang, Ming-Hsien Tu, Yi-Wei Chiu
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Patent number: 8325512Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.Type: GrantFiled: March 24, 2011Date of Patent: December 4, 2012Assignee: Faraday Technology Corp.Inventors: Ching-Te Chuang, Wei-Chiang Shih, Hung-Yu Lee, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Kun-Di Lee
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Patent number: 8320164Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.Type: GrantFiled: January 5, 2011Date of Patent: November 27, 2012Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Hao-I Yang, Mao-Chih Hsia, Yung-Wei Lin, Chien-Yu Lu, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Chia-Cheng Chen, Wei-Chiang Shih
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Patent number: 8259510Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.Type: GrantFiled: May 3, 2010Date of Patent: September 4, 2012Assignees: Faraday Technology Corp., National Chiao Tung UniversityInventors: Ching-Te Chuang, Hao-I Yang, Jihi-Yu Lin, Shyh-Chyi Yang, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Kun-Ti Lee, Hung-Yu Li