Patents by Inventor Ming-Hsin Yeh

Ming-Hsin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9230856
    Abstract: A method for manufacturing a structure having an air gap includes following steps. A plurality of patterns is formed in a pattern region of a substrate. A sacrificial layer is formed on the substrate, and a top surface of the sacrificial layer is lower than a top surface of the patterns to expose a plurality of upper portions of the patterns. A hard mask layer is formed to cover the sacrificial layer and the upper portions of the patterns. An etching-back process is performed to the hard mask layer to expose the sacrificial layer outside the pattern region, and the hard mask layer remaining inside the pattern region seals the opening between the upper portions of the patterns. The sacrificial layer is removed to form an air gap between the two adjacent patterns.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 5, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Ming-Hsin Yeh, Hsin Tai, Chan-Tsun Wu
  • Publication number: 20150270336
    Abstract: A method for manufacturing a structure having an air gap includes following steps. A plurality of patterns is formed in a pattern region of a substrate. A sacrificial layer is formed on the substrate, and a top surface of the sacrificial layer is lower than a top surface of the patterns to expose a plurality of upper portions of the patterns. A hard mask layer is formed to cover the sacrificial layer and the upper portions of the patterns. An etching-back process is performed to the hard mask layer to expose the sacrificial layer outside the pattern region, and the hard mask layer remaining inside the pattern region seals the opening between the upper portions of the patterns. The sacrificial layer is removed to form an air gap between the two adjacent patterns.
    Type: Application
    Filed: June 27, 2014
    Publication date: September 24, 2015
    Inventors: Ming-Hsin Yeh, Hsin Tai, Chan-Tsun Wu
  • Patent number: 7259097
    Abstract: A method for controlling an apparatus to perform a multi-layer chemical mechanical polishing (CMP) process with a polishing rate for a plurality of process runs. For each process run, a multilayered structure with a first thickness formed on a wafer is polished and a second thickness of the multilayered structure is predetermined to be polished away. The method comprises steps of receiving a post-CMP thickness information of the multilayered structure of a first process run, wherein for the first process run, the CMP process is performed for a first CMP process time. Then, a second CMP process time is determined according to the first CMP process time, the first thickness and the post-CMP thickness. Further, the second CMP process time is provided to the apparatus for processing a second process run posterior to the first process run.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: August 21, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Hsin Yeh, Cheng-Chuan Lee, Yi-Ching Wu, Chih-Hsiang Hsiao
  • Publication number: 20070062910
    Abstract: A complex CMP process is described. A target film is coarsely polished using a first polishing platen in a first CMP machine. The remaining target film is then fine polished using successively a second polishing platen and a third polishing platen in a second CMP machine that is different from the first CMP machine.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 22, 2007
    Inventors: Ming-Hsin Yeh, Cheng-Chuan Lee, Ming-Te Chen, Yi-Ching Wu, Chin-Hsiang Hsiao
  • Publication number: 20070062819
    Abstract: A method for controlling an apparatus to perform a multi-layer chemical mechanical polishing (CMP) process with a polishing rate for a plurality of process runs. For each process run, a multilayered structure with a first thickness formed on a wafer is polished and a second thickness of the multilayered structure is predetermined to be polished away. The method comprises steps of receiving a post-CMP thickness information of the multilayered structure of a first process run, wherein for the first process run, the CMP process is performed for a first CMP process time. Then, a second CMP process time is determined according to the first CMP process time, the first thickness and the post-CMP thickness. Further, the second CMP process time is provided to the apparatus for processing a second process run posterior to the first process run.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 22, 2007
    Inventors: Ming-Hsin Yeh, Cheng-Chuan Lee, Yi-Ching Wu, Chih-Hsiang Hsiao
  • Patent number: 5927385
    Abstract: The present invention relates to a cooling device for the CPU of computer, which is die-casting organic whole, basing on a base plate there is a set of radial radiating fins, the feature of the present invention is to build a raised heat block, lower than the radial radiating fins, upon the center of the radial radiating fins, and several equiangular guide radiation ribs are formed on the topside of the heat block laying from the center to the rim. In practising, the heat block absorbs more heat and by means of the guide radiation ribs lead and force splitting the strong cool air flow into branch currents through the radial radiating fins speedily to increase the efficiency of heat exchange.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: July 27, 1999
    Inventor: Ming Hsin Yeh
  • Patent number: D442120
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: May 15, 2001
    Inventor: Ming-Hsin Yeh
  • Patent number: D407714
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: April 6, 1999
    Inventor: Ming Hsin Yeh