Patents by Inventor Ming-Hsin Yu
Ming-Hsin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11790977Abstract: The present invention provides a memory controller including a plurality of channels. A first channel of the plurality of channels includes a first transmitter, a first pull-up variable resistor and a first pull-down variable resistor, wherein the first transmitter is configured to generate a first data signal to a memory module, the first pull-up variable resistor is coupled between a supply voltage and an output terminal of the first transmitter, and the first pull-down variable resistor is coupled to the output terminal of the first transmitter. The control circuit is coupled to the plurality of channels, and is configured to control the first pull-up variable resistor and/or the first pull-down variable resistor according to a reference voltage used by the memory module.Type: GrantFiled: June 17, 2021Date of Patent: October 17, 2023Assignee: MEDIATEK INC.Inventors: Chung-Hwa Wu, Ming-Hsin Yu
-
Publication number: 20220020419Abstract: The present invention provides a memory controller including a plurality of channels. A first channel of the plurality of channels includes a first transmitter, a first pull-up variable resistor and a first pull-down variable resistor, wherein the first transmitter is configured to generate a first data signal to a memory module, the first pull-up variable resistor is coupled between a supply voltage and an output terminal of the first transmitter, and the first pull-down variable resistor is coupled to the output terminal of the first transmitter. The control circuit is coupled to the plurality of channels, and is configured to control the first pull-up variable resistor and/or the first pull-down variable resistor according to a reference voltage used by the memory module.Type: ApplicationFiled: June 17, 2021Publication date: January 20, 2022Applicant: MEDIATEK INC.Inventors: Chung-Hwa Wu, Ming-Hsin Yu
-
Patent number: 9172376Abstract: One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors.Type: GrantFiled: May 28, 2013Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Ren Chen, Guang-Cheng Wang, Ming-Hsin Yu
-
Patent number: 8847658Abstract: An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor.Type: GrantFiled: January 31, 2013Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ming-Hsin Yu
-
Publication number: 20140266387Abstract: One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors.Type: ApplicationFiled: May 28, 2013Publication date: September 18, 2014Inventors: Yu-Ren Chen, Guang-Cheng Wang, Ming-Hsin Yu
-
Publication number: 20140062570Abstract: An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor.Type: ApplicationFiled: January 31, 2013Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Ming-Hsin Yu
-
Patent number: 8610488Abstract: A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.Type: GrantFiled: January 12, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsin Yu, Guang-Cheng Wang
-
Publication number: 20130181768Abstract: A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicant: Taiwan Semiconductror Manufacturing Co., Ltd.Inventors: Ming-Hsin YU, Guang-Cheng Wang
-
Patent number: 8436430Abstract: A circuit structure includes a first isolation region, and a first dummy gate electrode over and vertically overlapping the first isolation region. First pickup regions of a diode are formed on opposite sides of the first isolation region, wherein sidewalls of the first pickup regions contact opposite sidewalls of the first isolation region. Second pickup regions of the diode are formed on opposite sides of a combined region of the first pickup regions and the first isolation region, wherein the first and the second pickup regions are of opposite conductive types. A well region is under the first and the second pickup regions and the first isolation region, wherein the well region is of a same conductivity type as the second pickup regions.Type: GrantFiled: April 8, 2011Date of Patent: May 7, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hsin Yu, Kvei-Feng Yen
-
Publication number: 20120256292Abstract: A circuit structure includes a first isolation region, and a first dummy gate electrode over and vertically overlapping the first isolation region. First pickup regions of a diode are formed on opposite sides of the first isolation region, wherein sidewalls of the first pickup regions contact opposite sidewalls of the first isolation region. Second pickup regions of the diode are formed on opposite sides of a combined region of the first pickup regions and the first isolation region, wherein the first and the second pickup regions are of opposite conductive types. A well region is under the first and the second pickup regions and the first isolation region, wherein the well region is of a same conductivity type as the second pickup regions.Type: ApplicationFiled: April 8, 2011Publication date: October 11, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hsin Yu, Kvei-Feng Yen