Abstract: The present invention provides a fabrication method of an opening. The method includes providing a substrate having a conductive region therein. Thereafter, a dielectric layer is formed over the substrate and then a stacked layer is formed on the dielectric layer. The stacked layer includes a patterned metal hard mask layer, a patterned silicon oxynitride layer and a patterned silicon oxide layer on the dielectric layer in sequence. Afterward, a first portion of the dielectric layer is removed using the stacked layer as a first mask to form a first opening that exposes a surface of the conductive region.

Abstract: The present invention provides a fabrication method of an opening. The method includes providing a substrate having a conductive region therein. Thereafter, a dielectric layer is formed over the substrate and then a stacked layer is formed on the dielectric layer. The stacked layer includes a patterned metal hard mask layer, a patterned silicon oxynitride layer and a patterned silicon oxide layer on the dielectric layer in sequence. Afterward, a first portion of the dielectric layer is removed using the stacked layer as a first mask to form a first opening that exposes a surface of the conductive region.

Abstract: A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the substrate. The bottom antireflection layer, the silicon oxynitride layer and the metal hard mask layer that are not covered by the patterned photoresist layer are removed in a single process step, until a part of the surface of the dielectric layer is exposed. Thereafter, the patterned photoresist layer and the bottom antireflection layer are removed. Further using the silicon oxynitride layer and the metal hard mask layer as a mask, a portion of the dielectric layer and a portion of the barrier layer are removed to form a damascene opening that exposes the surface of the conductive line.

Abstract: A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the substrate. The bottom antireflection layer, the silicon oxynitride layer and the metal hard mask layer that are not covered by the patterned photoresist layer are removed in a single process step, until a part of the surface of the dielectric layer is exposed. Thereafter, the patterned photoresist layer and the bottom antireflection layer are removed. Further using the silicon oxynitride layer and the metal hard mask layer as a mask, a portion of the dielectric layer and a portion of the barrier layer are removed to form a damascene opening that exposes the surface of the conductive line.

Abstract: The present invention provides an integrated linear motor, which comprises a linear stage and a controller coupled to the linear stage, wherein the linear stage comprises a Hall sensor, an encoder, and a linear motor integrated thereon and the controller comprises a microprocessor, an amplifier, and a power supply integrated therein.

Abstract: A method for fabricating a single-damascene opening is described. The method includes providing a substrate having a conductive line formed therein. A barrier layer, a dielectric layer, a metal hard mask layer, a silicon oxynitride layer, a bottom antireflection layer and a patterned photoresist layer are sequentially formed on the substrate. The bottom antireflection layer, the silicon oxynitride layer and the metal hard mask layer that are not covered by the patterned photoresist layer are removed in a single process step, until a part of the surface of the dielectric layer is exposed. Thereafter, the patterned photoresist layer and the bottom antireflection layer are removed. Further using the silicon oxynitride layer and the metal hard mask layer as a mask, a portion of the dielectric layer and a portion of the barrier layer are removed to form a damascene opening that exposes the surface of the conductive line.

Abstract: A logic device for the transformation of the output of the RDC into series A-B pulses according to the present invention comprises: a chip with its two minimal bits (LSB-LSB-1) simulating as the clock source of A-B pulses, a signal-processing pin (BUSY) which output a TTL pulse wave as a control signal resource while LSB shifts from a low level to a high level and contrariwise, and a logic processing circuit as well as a buffer to output the displacement and velocity of a rotor in the form of A-B serial pulses.

Abstract: The present invention pertains to a via-first dual damascene process. A semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate is provided. The dielectric layer has a via opening exposing the conductive structure. The via opening is filled with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer. The GFP layer is etched back to a predetermined depth such that an exposed surface of the GFP layer is lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening. A surface treatment for altering surface property of the sidewalls and the exposed surface of the GFP layer is then carried out, thereby preventing a subsequent deep UV photoresist from interacting with the sidewalls or the exposed surface of the GFP layer either in a chemical or physical way.